A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design

Xu, Jingyu; Hong, Xianlong; Tong, Jing; Cai, Yici; Gu, Jun

doi:10.1145/1119772.1119958

Cited by 14 publications

(5 citation statements)

References 18 publications

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“…On the other hand, spacing usually can be increased only at the expense of netlength, which also has a negative effect on yield, power and timing. Recent papers on global routing (Xu et al [13], Jing et al [7], Ho et al [5]) propose heuristics partially adressing this tradeoff, but there is no approach yet that gives any performance guarantee (see [6] for a survey).…”

Section: Introductionmentioning

confidence: 99%

Optimizing yield in global routing

Müller

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We show that this algorithm can be used to optimize manufacturing yield. The core routine is a parallelized fully polynomial approximation scheme, scaling very well with the number of processors. We present results showing that our algorithm reduces the expected number of defects in wiring by more than 10 percent on state-of-the-art industrial chips.

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Section: Introductionmentioning

confidence: 99%

Optimizing yield in global routing

Müller

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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“…In general, detailed optimizations [11,12,18,25] have more definite relevant information but are normally restricted by global optimization results. In contrast, global level optimizations [29][30][31] have much greater flexibility on making changes but lack precise information for evaluating solution quality. When the coupling aware timing and the antenna problem are considered together with traditional design objectives, the high complexity of the problem implies that efforts need to be made in every step to provide a complete solution.…”

Section: Introductionmentioning

confidence: 99%

Coupling aware timing optimization and antenna avoidance in layer assignment

Mahapatra

2005

Proceedings of the 2005 International Symposium on Physical Design

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The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which consider only wire self capacitance become inadequate since the wire delay is affected more by coupling capacitance in ultra-deep submicron designs. Furthermore, the technology scaling dramatically increases the likelihood of the antenna problem in manufacturing and requests corresponding considerations in the routing stage. In this paper, we propose techniques that can be applied to handle the coupling aware timing and the antenna problem simultaneously during layer assignment which is an important step between global routing and detailed routing. An improved probabilistic coupling capacitance model is suggested for coupling aware timing optimization without performing track assignment. The antenna avoidance problem is modeled as a tree partitioning problem with a linear time optimal algorithm solution. This algorithm is customized to guide antenna avoidance in layer assignment. A linear time optimal jumper insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of ¾ ¼Ô× timing slack improvement validated by track assignment, ± antenna violation reduction and ± via violation reduction.

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“…However, the absence of wire adjacency information makes the coupling capacitance estimation hard to be obtained. A methodology level approach on coupling aware timing driven global routing is suggested in [15]. § This work is partially supported by SRC under contract 2003-TJ-1124.…”

Section: Introductionmentioning

confidence: 99%

Timing driven track routing considering coupling capacitance

Zhao

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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Abstract-As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven routing. In this paper, a coupling aware timing driven track routing heuristic is proposed. Given a global routing solution and timing constraint for each net, major trunks of wire segments are assigned to routing tracks such that the minimum timing slack among all nets is maximized. Delay penalties from both coupling capacitance and wire detour are considered in a unified graph model. The core problem is formulated and solved as a Sequential Ordering Problem (SOP). Routing blockages are handled in a post processing procedure. The experimental results on benchmark circuits show that the effect of coupling capacitance on timing is significant and the proposed heuristic results in greater improvement on coupling aware timing compared with other approaches.

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A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design

Cited by 14 publications

References 18 publications

Optimizing yield in global routing

Optimizing yield in global routing

Coupling aware timing optimization and antenna avoidance in layer assignment

Timing driven track routing considering coupling capacitance

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