Coupling aware timing optimization and antenna avoidance in layer assignment

Abstract

The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which consider only wire self capacitance become inadequate since the wire delay is affected more by coupling capacitance in ultra-deep submicron designs. Furthermore, the technology scaling dramatically increases the likelihood of the antenna problem in manufacturing and requests corresponding considerations in the routing stage. In this paper, we propose techniques that can be applied to handle the coupling aware timing and the antenna problem simultaneously during layer assignment which is an important step between global routing and detailed routing. An improved probabilistic coupling capacitance model is suggested for coupling aware timing optimization without performing track assignment. The antenna avoidance problem is modeled as a tree partitioning problem with a linear time optimal algorithm solution. This algorithm is customized to guide antenna avoidance in layer assignment. A linear time optimal jumper insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of ¾ ¼Ô× timing slack improvement validated by track assignment, ± antenna violation reduction and ± via violation reduction.

An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing

“…Since no previous work in the literature considers jumper insertion on a routing tree with obstacles, we extended the ISPD-05 work by Wu et al [12], the DAC-05 work [9] by Su and Chang, and the ISPD-04 work [4] jumpers. If the position for jumper insertion is in a forbidden region (an obstacle), we use the same optimal substitute presented in this paper to insert the jumper.…”

“…For this wire segment, the work in [4] needs two jumpers to fix the antenna violation (see Figure 3(a)) while a single jumper suffices for the work [9] to fix the violation (see Figure 3(b)). Another recent work [12] by Wu, Hu, and Mahapatra extends the work [4] to handle either a spanning or a Steiner tree. With the implementation scheme proposed by Kundu and Misra [7], the work [12] can achieve linear-time complexity for jumper insertion in a Steiner/spanning tree for antenna avoidance/fixing.…”

“…Another recent work [12] by Wu, Hu, and Mahapatra extends the work [4] to handle either a spanning or a Steiner tree. With the implementation scheme proposed by Kundu and Misra [7], the work [12] can achieve linear-time complexity for jumper insertion in a Steiner/spanning tree for antenna avoidance/fixing. To fix the antenna violation of a sink node (a gate terminal in this paper), the work first removes all subtrees around the node that violate the antenna rules.…”

“…As the routing-tree example shown in Figure 4(a), u1 and u2 are two sink nodes, the number beside each edge denotes the antenna charge weight (measured by the wire length, the wire area, and/or the wire perimeter), and the maximum antenna weight that a sink node can bear is assumed to be 10. For the work in [12], since we cannot partition the tree into any subtree with the total weight equal to 10, we will cut the heaviest edge near the sink node until the antenna rule is satisfied on u1 and u2. Thus, the edge e(u1, u2) = 10 will be removed first, and the work will insert four jumpers c1, c2, c3, and c4 as shown in Figure 4(b).…”

Wire density driven global routing for CMP variation and timing

“…rapidly with higher wire aspect ratio of the advanced technologies [2,26,27]. Therefore, interconnect delay will suffer from the increased resistance and coupling capacitance more seriously in the future.…”