A novel VLSI architecture for the real-time implementation of 2-D signal processing systems

This paper presents the block data flow architecture which is an alternative to the systolic array and the wavefront array for locally recursive algorithms such as those used for digital signal processing, image processing and matrix opemtions. The BDFA retains the advantageous features of a systolic array or a wavefront array such as regularity, modularity, and local interconnection. However, it uses a data partitioning strategy in addition to an algorithm partitioning strategy to reduce the data dependency, to decrease the interprocessor communication requirements, and to decrease. the hardware complexity compared to systolic and wave front arrays. The BDFA also uses block data processing and the block data flow paradigm to minimize system management overhead due to communication protocols. Thus, the processors in a BDFA operate efficiently to achieve a system with a high throughput and a high efficiency.

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A programmable simulator for analyzing the block data flow architecture

Alexandre

Alexander

Reeves

Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems

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A programmable simulator has been developed f o r analyzing the performance of a class of parallel computers. The simulator provides detailed information about the timing, resource usage, and output results f o r an algorithm ezecuting on the parallel computer. A user specifies the configuration and performance characteristics of the computer to be simulated. The user also describes the algorithm to be ezecuted on the computer. The use of the simulator for QR factorization is briefly described and the results are presented. Our approach is compared with other simulation methods.

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A novel VLSI architecture for the real-time implementation of 2-D signal processing systems

Cited by 13 publications

References 6 publications

Parallel image processing with the block data parallel architecture

Parallel image processing with the block data parallel architecture

A high performance architecture for real-time signal processing and matrix operations

A programmable simulator for analyzing the block data flow architecture

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