A novel VLSI solution to a difficult graph problem

Chakradhar, Srimat; Agrawal, Vishwani D.

doi:10.1109/isvd.1991.185104

Cited by 6 publications

(4 citation statements)

References 7 publications

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“…Several studies have implemented graphs algorithms by direct construction in hardware [25]. For example, directional graphs have been represented as adjacency matrix in hardware and a direct construction has been used to encode the input graph's connectivity as a static circuit [26]. Recently, attracted by the application-specific performance of FPGA devices, researchers have implemented several well-known graph algorithms in FPGAs to speed up their execution [27].…”

Section: B Logic Implementationmentioning

confidence: 99%

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Bai

Alawad

Riera

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Being "memory-centric", the single-chip distributed logic-memory (DLM) architecture can significantly improve the overall performance and energy efficiency of many memoryintensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an FPGA designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chip and off-chip memory. In this paper, we offer our solutions to both of these challenges. Specifically, 1) we propose a stochastic memory partitioning scheme based on the well-known simulated annealing algorithm. It obtains memory partitioning solutions that promote parallelized memory accesses by exploring large solution space; 2) we augment the proposed DLM architecture with a reconfigure hardware graph that can dynamically compute precedence relationship between memory partitions, thus effectively exploiting algorithmic level memory parallelism on a per-application basis.We evaluate the effectiveness of our approach (A3) against two other DLM architecture synthesizing methods: an algorithmiccentric reconfigurable computing architectures with a single monolithic memory (A1) and the heterogeneous distributed architectures synthesized according to [1] (A2). To make our comparison fair, in all three architectures, the data path remains the same while local memory architecture differs. For each of ten benchmark applications from SPEC2006 and MiBench [2], we break down the performance benefit of using A3 into two parts: the portion due to stochastic local memory partitioning and the portion due to the dynamic graph-based memory arbitration. All experiments have been conducted with a Virtex-5 (XCV5LX155T-2) FPGA. On average, our experimental results show that our proposed A3 architecture outperforms A2 and A1 by 34% and 250%, respectively. Within the performance improvement of A3 over A2, more than 70% improvement comes from the hardware graph-based memory scheduling.

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Section: B Logic Implementationmentioning

confidence: 99%

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Bai

Alawad

Riera

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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“…Graphs represented as its adjacency matrix in hardware and the glue logic and interconnect which implement a particular algorithm. Chakradhar and Agrawal [3] use a direct construction to encode the input graph's connectivity as a static circuit. Whereas, J. Babb, M. Prank, and A. Agarwal [4] reported graph-circuit transformations for closed semiring problems: shortest path and transitive closure.…”

Section: Motivationmentioning

confidence: 99%

Implementation of Graph Algorithms in Reconfigurable Hardware (FPGAs) to Speeding Up the Execution

Ahmed

Alam

Rahman

et al. 2009

2009 Fourth International Conference on Computer Sciences and Convergence Information Technology

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This paper focus on hardware representation and implementation of graph algorithms in Reconfigurable Hardware (FPGAs) to speeding up the execution. Generally, Software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.

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“…Individual details of the two prior static approaches are as follows. Chakradhar and Agrawal [3] described a graph-circuit transformation for computing a graph's independent sets. They use a direct construction (c/.…”

Section: Related Work and Comparison To Softwarementioning

confidence: 99%

“…Compiling graphs into specialized hardware circuits in order to attain rapid property computation was initially proposed for integrated circuits [3] and then more directly for reconfigurable hardware arrays [1]. Section 3 contains a direct construction similar to those of the prior work.…”

Section: Introductionmentioning

confidence: 99%

A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms

Huelsbergen¹

2000

Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays

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This paper gives a representation for graph data structures as electronic circuits in reconfigurable hardware. Graph properties, such as vertex teachability, are computed quickly by exploiting a graph's edge parallelism--signals propagate along many graph edges concurrently. This new representation admits arbitrary graphs in which vertices/edges may be inserted and deleted dynamically at low cost--graph modification does not entail any re-fitting of the graph's circuit. Dynamic modification is achieved by rewriting cells in a reconfigurable hardware array. Dynamic graph algorithms are given for vertex reachability, transitive closure, shortest unit path, cycle detection, and connected-component identification. On the task of computing a graph's transitive closure, for example, simulation of such a dynamic graph processor indicates possible speedups greater than three orders of magnitude compared to an efficient software algorithm running on a contemporaneously fast uniprocessor. Implementation of a prototype in an FPGA verifies the accuracy of the simulation and demonstrates that a practical and efficient (compact) mapping of the graph construction is possible in existing FPGA architectures. In addition to speeding conventional graph computations with dynamic graph processors, we note their potential as parallel graph reducers implementing general (Turing equivalent) computation.

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A novel VLSI solution to a difficult graph problem

Cited by 6 publications

References 7 publications

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Implementation of Graph Algorithms in Reconfigurable Hardware (FPGAs) to Speeding Up the Execution

A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms

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