A novel write-scheme for data integrity in memristor-based crossbar memories

Koldehofe

2022

IEEE Access

The high performance requirements of nowadays computer networks are limiting their ability to support important requirements of the future. Two important properties essential in assuring cost-efficient computer networks and supporting new challenging network scenarios are operating energy efficient and supporting cognitive computational models. These requirements are hard to fulfill without challenging the current architecture behind network packet processing elements such as routers and switches. Notably, these are currently dominated by the use of traditional transistor-based components. In this article, we contribute with an in-depth analysis of alternative architectural design decisions to improve the energy footprint and computational capabilities of future network packet processors by shifting from transistor-based components to a novel component named Memristor. A memristor is a computational component characterized by non-volatile operations on a physical state, mostly represented in form of (electrical) resistance. Its state can be read or altered by input signals, e.g. electrical pulses, where the future state always depends on the past state. Unlike in traditional von Neumann architectures, the principles behind memristors impose that memory operations and computations are inherently colocated. In combination with the non-volatility, this allows to build memristors at nanoscale size and significantly reduce the energy consumption. At the same time, memristors appear to be highly suitable to model cognitive functionality due to the state dependence transitions in the memristor. In cognitive architectures, our survey contributes to the study of memristorbased Ternary Content Addressable Memory (TCAM) used for storage of cognitive rules inside packet processors. Moreover, we analyze the memristor-based novel cognitive computational architectures built upon self-learning capabilities by harnessing from non-volatility and state-based response of memristors (including reconfigurable architectures, reservoir computation architectures, neural network architectures and neuromorphic computing architectures).

Section: Data Write Operation In Tcammentioning

confidence: 99%

“…Hybrid architectures [97] Electronic neurons [100] Von Neumann vs Neuromorphic arch. [110] Write operation [70] Dynamic route prefix memories [49][50]…”

Section: Architectures Reservoir Computation Memristive Propertiesmentioning

confidence: 99%

On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network Functions

Koldehofe

2022

IEEE Access

“…Many prior researches have focused over the use of memristors for the development of energy efficient TCAM architectures. Some of the research areas in the design of memristor-based TCAM architecture include TCAM cell designing [4], managing storage operations [5], [6], performing search functions [7] and computing read and write operations efficiently [1]. The studies in these research areas showcased the effectiveness of memristors in conserving energy at the same processing rate of one clock cycle.…”

Section: Background and Related Workmentioning

confidence: 99%

Towards Energy Efficient Memristor-based TCAM for Match-Action Processing

2022 IEEE 13th International Green and Sustainable Computing Conference (IGSC)

Goossens

Banerjee

et al. 2022

Match-action processors play a crucial role of communicating end-users in the Internet by computing network paths and enforcing administrator policies. The computation process uses a specialized memory called Ternary Content Addressable Memory (TCAM) to store processing rules and use header information of network packets to perform a match within a single clock cycle. Currently, TCAM memories consume huge amounts of energy resources due to the use of traditional transistor-based CMOS technology. In this article, we motivate the use of a novel component, the memristor, for the development of a TCAM architecture. Memristors can provide energy efficiency, nonvolatility, and better resource density as compared to transistors. We have proposed a novel memristor-based TCAM architecture built upon the voltage divider principle for energy efficient matchaction processing. Moreover, we have tested the performance of the memristor-based TCAM architecture using the experimental data of a novel Nb-doped SrTiO 3 memristor. Energy analysis of the proposed TCAM architecture for given memristor shows promising power consumption statistics of 16 µW for a match operation and 1 µW for a mismatch operation.

“…They proposed a fuzzy look up functionality to measure the memristor states in the M-CAM architecture. In [26], Ruotolo et al addressed the search operation challenges in the memristor-based TCAM. They showed that the memristor-based TCAM can provide power efficiency at the cost of less precision in the data storage mode as compared to the PCMs and magnetic memories.…”

Section: Related Workmentioning

confidence: 99%

TCAmM^CogniGron: Energy Efficient Memristor-Based TCAM for Match-Action Processing

2022 IEEE International Conference on Rebooting Computing (ICRC)

Goossens

Banerjee

et al. 2022

The Internet relies heavily on programmable matchaction processors for matching network packets against locally available network rules and taking actions, such as forwarding and modification of network packets. This match-action process must be performed at high speed, i.e., commonly within one clock cycle, using a specialized memory unit called Ternary Content Addressable Memory (TCAM). Building on transistorbased CMOS designs, state-of-the-art TCAM architectures have high energy consumption and lack resilient designs for incorporating novel technologies for performing appropriate actions. In this article, we motivate the use of a novel fundamental component, the 'Memristor', for the development of TCAM architecture for match-action processing. Memristors can provide energy efficiency, non-volatility and better resource density as compared to transistors. We have proposed a novel memristorbased TCAM architecture called TCAmM CogniGron , built upon the voltage divider principle and requiring only two memristors and five transistors for storage and search operations compared to sixteen transistors in the traditional TCAM architecture. We analyzed its performance over an experimental data set of Nbdoped SrTiO 3 -based memristor. The analysis of TCAmM CogniGron showed promising power consumption statistics of 16 µW and 1 µW for match and mismatch operations along with twice the improvement in resources density as compared to the traditional architectures.