A novel zero-aware read-static-noise-margin-free SRAM cell for high density and high speed cache application

Mazreah, Arash Azizi; Shalmani, Mohammad Taghi Manzuri; Noormandi, R.; Mehrparvar, Ali

doi:10.1109/icsict.2008.4734683

Cited by 3 publications

(4 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [1] from the execution traces of the SPEC2000 benchmarks around 85% of the instruction write bits are '0' and over 90% of the data write bits are '0'. Also over 70% of the bits that are read from the cache are zeros [4]. Based on these observations we simulated average dynamic power consumption in a cache access using HSPICE in 65-nm PTM.…”

Section: Experimental Results and Dynamic Power Consumptionmentioning

confidence: 99%

See 1 more Smart Citation

A low power and high density cache memory based on novel SRAM cell

Mazreah

Romani²,

Manzuri

et al. 2009

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell, respectively.

show abstract

Section: Experimental Results and Dynamic Power Consumptionmentioning

confidence: 99%

“…3)-Sensing: After word-line1 deactivate the sense amplifier is enabled to read data on BLB. This new cell uses sense amplifier that introduced in [4,5]. 4)-Idle mode: At the end of read operation, cell will go to idle mode and BLB asserted to V DD .…”

Section: Write and Read Operation On Cellmentioning

confidence: 99%

A low power and high density cache memory based on novel SRAM cell

Mazreah

Romani²,

Manzuri

et al. 2009

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

show abstract

“…x If the ST node voltage is high, the BL voltage and ST node equalized.After the deactivation of WL, the sense amplifier is turned ON to read the data on BL [9][10].…”

Section: A Write/read Operationsmentioning

confidence: 99%

Enhancement of Parameters for 7T SRAM Cell in Nanometer Era

Akashe

Rajak

Sharma

et al. 2012

2012 Second International Conference on Advanced Computing &Amp; Communication Technologies

View full text Add to dashboard Cite

As the technology scales down to 90nm and below, leakage current/ power is becoming one of the most critical concerns for low power applications. 40% or even higher percentage of the total power consumption is waste due to the leakage of the transistors. This paper compares the performance of two SRAM cell topologies, which includes the conventional 6T-cell and the 7T-cell.In particular the static noise margin (SNM) of each cell designed is examined. The conventional six transistors SRAM (6T) suffered from the external noise because they have direct paths through bit-line (BL) to their storage nodes. This paper proposes 7T SRAM cell which has no direct paths through bit-line (BL) to the data storage nodes and has higher endurance against external noise. The proposed 7T-cell is composed of two separate data access mechanisms; one is for the write one and another is for read. Here we examined the difference between the power consumption of both 6T and 7T cell and also find out which cell works better on low power.

show abstract

“…These on-chip caches are usually implemented using arrays of SRAM cells. A six transistor SRAM cell is conventionally used as the memory cell [4]. However, the mismatch in the strength between transistors of 6T SRAM cell due to process variations can results failure during read operation (flipping of the cell data while reading) [2], especially at low-V DD level [3].…”

Section: Introductionmentioning

confidence: 99%

A Nanoscale CMOS SRAM Cell for High Speed Applications

Mazreah

Shalmani

Mehrparvar

2009

2009 Fifth International Conference on MEMS NANO, and Smart Systems

Self Cite

View full text Add to dashboard Cite

The leakage current and process variation are drastically increased with technology scaling. In Conventional SRAM cell due to process variations, stored data can be destroyed during read operation. Therefore, leakage current of SRAM cell and stability during read operation are two important parameters in nano-scaled CMOS technology. To overcome these limitations and to increase the speed of conventional SRAMs, we have developed a read-static-noisemargin-free SRAM cell. The developed cell has six-transistors and uses two read/write-lines and two read/write-bit-lines during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The leakage current of new cell is 52% smaller than a conventional six-transistor SRAM cell. Simulation results shows proposed cell has correct operation during read/write and idle modes and is 45% faster than a usual six-transistor SRAM cell.

show abstract

A novel zero-aware read-static-noise-margin-free SRAM cell for high density and high speed cache application

Cited by 3 publications

References 8 publications

A low power and high density cache memory based on novel SRAM cell

A low power and high density cache memory based on novel SRAM cell

Enhancement of Parameters for 7T SRAM Cell in Nanometer Era

A Nanoscale CMOS SRAM Cell for High Speed Applications

Contact Info

Product

Resources

About