A NUCA Substrate for Flexible CMP Cache Sharing

Abstract

We propose an organization for the on-chip memory system of a chip multiprocessor in which 16 processors share a 16-Mbyte pool of 64 level-2 (L2) cache banks. The L2 cache is organized as a nonuniform cache architecture (NUCA) array with a switched network embedded in it for high performance. We show that this organization can support a spectrum of degrees of sharing: unshared, in which each processor owns a private portion of the cache, thus reducing hit latency, and completely shared, in which every processor shares the entire cache, thus minimizing misses, and every point in between. We measure the optimal degree of sharing for different cache bank mapping policies and also evaluate a per-application cache partitioning strategy. We conclude that a static NUCA organization with sharing degrees of 2 or 4 works best across a suite of commercial and scientific parallel workloads. We demonstrate that migratory dynamic NUCA approaches improve performance significantly for a subset of the workloads at the cost of increased complexity, especially as per-application cache partitioning strategies are applied. We also evaluate the energy efficiency of each design point in terms of network traffic, bank accesses, and external memory accesses.

A power-efficient migration mechanism for D-NUCA caches

“…This work, instead, focuses on the dynamic power consumption caused by bank accesses in a D-NUCA architecture, and aims to optimize the migration mechanism in order to make it more energy efficient without impacting on performance. Huh et al [8] proposed a CMP D-NUCA architecture and evidenced how two or more processors which share a cache line can generate migration patterns similar to the one presented in this work, but a study on the relevance of this phenomenon depending on the application and the architecture is not presented.…”

Improving last level shared cache performance through mobile insertion policies (MIP)

“…L2 maintains the same associativity but is 256 kB. Finally, LLC configuration corresponds to a shared SNUCA [29] with 4 banks and a total capacity of 8 MB. L2 is exclusive with L1 (i.e., acts as a victim cache of L1) and LLC is inclusive with private caches [28].…”

Energy Efficiency of a Multi-Core Processor by Tag Reduction

“…[10] proposes a new thinking to use multi-core to sequential applications that spills cores. [11] does the research on flexible CMP cache sharing. It offers a structure in which L2 caches may be shared by all processors, may be separated into private per-processor partitions, or may be partitioned into separate caches, each shared by a subset of the processors.…”