A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing

Abstract

We propose a parallel and randomized algorithm to solve the problem of discrete dual-Vt assignment combined with continuous gate sizing which is an important low power design technique in high performance domains. This combinatorial optimization problem is particularly difficult to solve on large-sized circuits. We first introduce a hybrid algorithm which combines the existing heuristics and convex formulations for this problem to achieve a better tradeoff between the runtime of the algorithm and the quality of generated solution. We then extend our algorithm to include parallelism and randomization. We introduce a unique utilization of parallelism to better identify the optimization direction. Consequently, we can reduce both the number of iterations in optimization as well as improve the quality of solution. We further use random sampling to avoid being trapped in local minima and to focus the optimization effort on the more "promising" regions of the solution space. Our algorithm improves the average power by 37% compared to an approach which is based on solving a continuous convex program and applying discretization. Power improvement is over 50% for larger benchmarks for an implementation on a grid of 9 computers.

A new algorithm for simultaneous gate sizing and threshold voltage assignment

“…When leakage power becomes prominent, people start to use gates with different threshold voltage (V t ) levels in order to trade timing slack for leakage power reduction [6][7][8]. Due to the similarity between them, gate/transistor sizing and V t assignment are often conducted simultaneously [9][10][11][12][13][14]. Among these previous works, [6] and [12] are greedy or sensitivity driven heuristics.…”

“…In [7,13], continuous optimization is performed and then the results are rounded to obtain discrete solutions. The work of [14] exploits parallelism in discrete V t assignment and continuous gate sizing. In [11], it is found that linear programming based optimization often results in discrete V t assignment solutions and therefore the rounding can be skipped.…”

Strategic Optimization Techniques For FRTU Deployment and Chip Physical Design

“…However, it will result in the significant degradation of circuit delay compared to the obtained continuous gate sizing solution [56,58]. This motivates some recent works to design combinatorial algorithms which directly handle discrete gate size, such as a continuous solution guided dynamic programming technique in [56], a network-flow based approach in [59], a parallelization and randomization based technique in [60], and a multi-dimensional gradient descent based algorithm in [61]. These algorithms are effective, however, they are all heuristics without any theoretical guarantee on the quality of their discrete gate sizing solutions.…”