A Parallel-friendly Majority Gate to Accelerate In-memory Computation

Abstract

Efforts to combat the 'von Neumann bottleneck' have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it's expressive power. In this work, we propose a method to compute majority while reading from a transistoraccessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs' resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively. Index Terms-Resistive RAM (RRAM), majority logic, majority gate, memristor, 1 Transistor-1 Resistor(1T-1R), von Neumann bottleneck, in-memory computing, compute-in-memory, processing-in-memory, parallel-prefix adder This is author's version of the accepted paper. For the published paper, see the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) proceedings in https://ieeexplore.ieee.org/ See Conference presentation (20 min video) at https://asap2020.cs.manchester.ac.uk/paper.php?id=72

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

“…Table I lists the truth table of 3-input majority gate (M 3 (A, B, C)) and the effective resistance for all the eight possibilities. To verify the proposed gate on a real ReRAM device, we choose the 1T-1R cell from IHP 1 . The 1T-1R structure consists of a NMOS transistor having a (W/L) of (150 nm/130 nm).…”

“…11. The steps are 1) Majority at col. (1,9,26,33,42,49,58,65). In the above mapping, it must be noted that each bitwise majority operation is a READ operation and it must be followed by WRITE to be used as an input to the next logic level.…”

Design of In-Memory Parallel-Prefix Adders

“…Consequently, it is beneficial to express the adder using one logic primitive, rather than four different logic primitives. Recently, an in-memory majority gate was proposed in [31,32]. The three inputs to the majority gate are the three resistances of the memory cells, and the output majority is computed as a READ operation (Figure 3a).…”

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

“…Logic [5] small area ternary logic However, besides those key advantages, there are several issues regarding this technology, which have to be addressed in order to make it competitive as a data storage device. Reliability is one of the biggest concerns in order to avoid data loss [8].…”

“…They are used as analog elements in neuromorphic circuits [1], used as a general non-volatile memory device [2,3] or in non-volatile logic gates [4]. Those last two applications can also be combined to realize in-memory computing, one prominent way to overcome the von Neumann bottleneck, one of the major challenges for further improvements of modern computing systems [5]. Furthermore, due to the probabilistic nature of the physical switching inside the RRAM devices, they can also be used in security applications to enable the generation of physical unclonable functions (PUFs) [6].…”