A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

Pechmann, Stefan; Mai, Timo; Völkel, Matthias; Mahadevaiah, Mamathamba Kalishettyhalli; Pérez, Eduardo; Quesada, Emilio Pérez-Bosch; Reichenbach, Marc; Wenger, Christian; Hagelauer, Amelie

doi:10.3390/electronics10050530

Cited by 6 publications

(2 citation statements)

References 21 publications

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“…A triple-row decoder is used which uses MAJ as control signal to switch between majority operation (three rows selected) and normal READ/WRITE operation (single row is selected). and LRS = 10.5 kΩ [36]. For such a device, the sensing window for majority gate = R 001 ef f − R 011 ef f = 9.5 k -5.1 kΩ = 4.4 kΩ (see Section III-B).…”

Section: Maj Enmentioning

confidence: 99%

“…The Stanford-PKU model which is a physicsbased model was used to model the filamentary switching mechanism. The algorithm proposed in [39] was used to exactly fit the model to the characteristics of IHP's 1T-1R cell [36] (HRS= 200 kΩ and LRS=10.5 kΩ, V SET = 0.8 V, V RESET = -1.1 V). Following the mapping described in Section V-B, the functionality of a 4-bit in-memory multiplier was verified by executing a sequence of READ (Majority), and WRITE operations.…”

Section: Simulation Of 4×4 Wallace Tree Multiplier In 1t-1r Arraymentioning

confidence: 99%

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A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

Lakshmi

Reuben

Pudi

2022

IEEE Trans. Circuits Syst. I

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In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the 'von Neumann bottleneck' and strengthens the present research impetus to overcome the memory wall. While many methods have been recently proposed to implement Boolean logic in memory, the latency of arithmetic circuits (adders and consequently multipliers) implemented as a sequence of such Boolean operations increases greatly with bit-width. Existing in-memory multipliers require O(n 2 ) cycles which is inefficient both in terms of latency and energy. In this work, we tackle this exorbitant latency by adopting Wallace Tree multiplier architecture and optimizing the addition operation in each phase of the Wallace Tree. Majority logic primitive was used for addition since it is better than NAND/NOR/IMPLY primitives. Furthermore, high degree of gate-level parallelism is employed at the array level by executing multiple majority gates in the columns of the array. In this manner, an in-memory multiplier of O(n.log(n)) latency is achieved which outperforms all reported in-memory multipliers. Furthermore, the proposed multiplier can be implemented in a regular transistor-accessed memory array without any major modifications to its peripheral circuitry and is also energyefficient.

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Section: Maj Enmentioning

confidence: 99%

Section: Simulation Of 4×4 Wallace Tree Multiplier In 1t-1r Arraymentioning

confidence: 99%

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

Lakshmi

Reuben

Pudi

2022

IEEE Trans. Circuits Syst. I

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Efficient in situ learning of hybrid LIF neurons using WTA mechanism for high-speed low-power neuromorphic systems

Hussain,

Prasad V,

Sanki

2024

Phys. Scr.

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The emerging market for hardware neuromorphic systems has fulfilled the growing demand for fast and energy-efficient computer architectures. Memristor-based neural networks are a viable approach to meet the need for low-power neuromorphic devices. Spiking neural networks (SNNs) are widely recognized as the best hardware solution for mimicking the brain’s efficient processing capabilities. To build the SNN model, we have designed an energy-efficient hybrid Leaky Integrated and Fire (LIF) neuron model using Carbon Nano Tube Field Effect Transistors (CNTFET) and memristors. This hybrid neuron operates at 3.89 MHz, with 1.047nW and 0.257fJ of power and energy per spike with a constant power supply (V dd ) and an excitation voltage of 0.5V, under the ideal conditions. When the intrinsic constraints of CNTFETs and memristors, such as parasitic elements and hysteresis effects, are taken into consideration, the operating frequency is lowered to 3.45 MHz (an 11.5% decrease), and energy consumption rises to 0.317 fJ per spike (a 23.3% increase). Despite these limitations, our design outperforms with existing works. On the other hand the development of in situ, Spike Timing Dependent Plasticity (STDP) learning through memristors as synapses results in a computational challenge. In this paper, we adopt a potent technique capable of carrying out both learning and inference. The weight modulation is accomplished using a linear memristor model, resulting in high speed and reduced power consumption. We intend to apply the winner-takes-all (WTA) mechanism within the SNN architecture, which incorporates recurrently connected proposed neurons in the output layer, for real-time pattern recognition. The proposed design has been implemented and the performance metrics superseded the existing works in terms of power, energy, and accuracy. Furthermore, the design is capable of classifying 50×104 images per second.

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Memristive-based in-memory computing: from device to large-scale CMOS integration

Quesada

Pérez

Mahadevaiah

et al. 2021

Neuromorph. Comput. Eng.

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With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO 2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal–insulator–metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.

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A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

Cited by 6 publications

References 21 publications

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

Efficient in situ learning of hybrid LIF neurons using WTA mechanism for high-speed low-power neuromorphic systems

Memristive-based in-memory computing: from device to large-scale CMOS integration

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