Training and recognition with neural networks generally require high throughput, high energy efficiency, and scalable circuits to enable artificial intelligence tasks to be operated at the edge, i.e., in battery-powered portable devices and other limited-energy environments. In this scenario, scalable resistive memories have been proposed as artificial synapses thanks to their scalability, reconfigurability, and high-energy efficiency, and thanks to the ability to perform analog computation by physical laws in hardware. In this work, we study the material, device, and architecture aspects of resistive switching memory (RRAM) devices for implementing a 2-layer neural network for pattern recognition. First, various RRAM processes are screened in view of the device window, analog storage, and reliability. Then, synaptic weights are stored with 5-level precision in a 4 kbit array of RRAM devices to classify the Modified National Institute of Standards and Technology (MNIST) dataset. Finally, classification performance of a 2-layer neural network is tested before and after an annealing experiment by using experimental values of conductance stored into the array, and a simulation-based analysis of inference accuracy for arrays of increasing size is presented. Our work supports material-based development of RRAM synapses for novel neural networks with high accuracy and low-power consumption.

Filament-type HfO2-based RRAM has been considered as one of the most promising candidates for future non-volatile memories. Further improvement of the stability, particularly at the “OFF” state, of such devices is mainly hindered by resistance variation induced by the uncontrolled oxygen vacancies distribution and filament growth in HfO2 films. We report highly stable endurance of TiN/Ti/HfO2/Si-tip RRAM devices using a CMOS compatible nanotip method. Simulations indicate that the nanotip bottom electrode provides a local confinement for the electrical field and ionic current density; thus a nano-confinement for the oxygen vacancy distribution and nano-filament location is created by this approach. Conductive atomic force microscopy measurements confirm that the filaments form only on the nanotip region. Resistance switching by using pulses shows highly stable endurance for both ON and OFF modes, thanks to the geometric confinement of the conductive path and filament only above the nanotip. This nano-engineering approach opens a new pathway to realize forming-free RRAM devices with improved stability and reliability.

In this report, we propose an effective route to reduce the cell-to-cell variability in 1T-1R based RRAM arrays by combining the excellent switching performance of Hf1-xAlxOy with an optimized Incremental Step Pulse with Verify Algorithm (ISPVA) for programming. The strongly reduced cell-to-cell variability improves the thermal and post-programming stability of the arrays, which is relevant for many applications of the RRAM technology. Finally, the retention study at 150 °C enables the prediction of the data storage capability.

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Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 • C.