Reduction of the Cell-to-Cell Variability in Hf1-xAlxOyBased RRAM Arrays by Using Program Algorithms

Pérez, Eduardo; Grossi, Alessandro; Zambelli, Cristian; Olivo, P.; Roelofs, Robin; Wenger, Christian

doi:10.1109/led.2016.2646758

Cited by 51 publications

(35 citation statements)

References 10 publications

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“…For this transistor, the minimal NMOS transistor with a gate length of 130 nm and a gate width of 150 nm is used. In previous publications of this technology, the RRAM cells were fabricated in the 250 nm process SGB25V from IHP, containing a selection transistor of different dimensions [11,12]. For scaling reasons, the cells were migrated to the SG13S process.…”

Section: T1r Rram Cellsmentioning

confidence: 99%

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

et al. 2021

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In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

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Section: T1r Rram Cellsmentioning

confidence: 99%

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

et al. 2021

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“…One can easily observe that the RESET voltage varies from as low as -0.5 V to -1.25 V while the high resistance state (HRS) varies from 66.66 KΩ to as high as 100 MΩ, among a random sample of RRAMs. Each of these RRAMs have been optimized in some manner: the RRAM device in [11] have been optimized for less cell-to-cell variability (in the array) and post-programming instabilities; [12] optimizes cycle-to-cycle and cell-to-cell variability; [10], [12] have the advantage of a high resistance window and [13] reports less HRS variability in addition to a high resistance window. How can one model RRAMs with such varied attributes?…”

Section: B Diversity In Rram Characteristicsmentioning

confidence: 99%

“…To corroborate our modeling approach, we used the 4k bit 1T-1R array fabricated at IHP [11]. The 1T-1R is constituted by a NMOS transistor manufactured in IHP's 0.25 µm CMOS technology, whose drain is connected in series to the RRAM.…”

Section: E Model Corroborationmentioning

confidence: 99%

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A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability

Reuben

Fey

Wenger

2019

IEEE Trans. Nanotechnology

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Modeling of Resistive RAMs (RRAMs) is a herculean task due to its non-linearity. While the exigent need for a model has motivated research groups to formulate realistic models, the diversity in RRAMs' characteristics has created a gap between model developers and model users. This paper bridges the gap by proposing an algorithm by which the parameters of a model are tuned to specific RRAMs. To this end, a physicsbased compact model was chosen due to its flexibility, and the proposed algorithm was used to exactly fit the model to different RRAMs, which differed greatly in their material composition and switching behavior. Further, the model was extended to simulate multiple Low Resistance States (LRS), which is a vital focus of research to increase memory density in RRAMs. The ability of the model to simulate the switching from a high resistance state to multiple LRS was verified by measurements on 1T-1R cells.

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“…Therefore, developing low temperature ALD technique (eg, 130°C) is an effective path to realize flexible RRAM networks. HfAlOx is a kind of attractive dielectric that could be deposited by ALD, showing great potential in neuromorphic computing devices and wearable electronics 22,23 …”

Section: Introductionmentioning

confidence: 99%

Flexible 3D memristor array for binary storage and multi‐states neuromorphic computing applications

Wang

Meng

Chen

et al. 2020

InfoMat

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The demand of flexible neuromorphic computing electronics is increasing with the rapid development of wearable artificial intelligent devices. The flexible resistive random‐access memory (RRAM) is one excellent candidate of high‐density storage devices. However, due to the limitations of fabrication process, materials system and device structure, it is difficult to prepare flexible 3D high‐density network for neuromorphic computing. In this paper, a 3D flexible memristors network is developed via low‐temperature atomic layer deposition (ALD) at 130°C, with potential of extending to various flexible electronics. The typical bipolar switching characteristics are verified in RRAM units of 3D network, including first, second and third layers. Besides binary storage, the multibit storage in single unit is demonstrated and the storage density is further increased. As a connection link between binary storage and brain‐inspired neuromorphic computing, the multibit storage capability paves the way for the tunable synaptic plasticity, for example, long‐term potentiation/depression (LTP/LTD). The 3D memristors network successfully mimicked the typical neuromorphic functionality and realized ultra‐multi conductance states modulation under 600 spikes. The robust mechanical flexibility is further demonstrated via LTP/LTD emulation under bending states (radius = 10 mm). The 3D flexible memristors network shows significant potential of applications in high‐performance, high‐density and reliable wearable neuromorphic computing system.

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Reduction of the Cell-to-Cell Variability in Hf_1-xAl_xO_yBased RRAM Arrays by Using Program Algorithms

Cited by 51 publications

References 10 publications

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability

Flexible 3D memristor array for binary storage and multi‐states neuromorphic computing applications

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