Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention

Pérez, Eduardo; Zambelli, Cristian; Mahadevaiah, Mamathamba Kalishettyhalli; Olivo, P.; Wenger, Christian

doi:10.1109/jeds.2019.2931769

Cited by 56 publications

(33 citation statements)

References 36 publications

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“…As stated before, the I-V curves shown in Figure 3a,b are median values. Previous measurements of this RRAM technology indicate a non-negligible amount of variability [9,15]. Especially the set and reset voltages can vary up to 1 V. Furthermore, the change of the electrical properties can be observed during cycling and temperature variations.…”

Section: Cell Variabilitymentioning

confidence: 86%

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

et al. 2021

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In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

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Section: Cell Variabilitymentioning

confidence: 86%

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

et al. 2021

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“…This is possible due to the multilevel approach also known as Multi-Level Cell (MLC) behavior, consisting of modulating in multiple states the resistance/conductance of the dielectric layer in the RRAM cell. To obtain the mentioned MLC behavior, different programming techniques have been reported lately, such as gradual Reset process by consecutive identical pulses [9], applying positive and negative voltage sweeps with different stop values during the Set and Reset operations [10][11][12], modifying the compliance current imposed to the cell during the Set transition [13][14][15] and implementing multilevel incremental step pulses with verify algorithm (M-ISPVA) [16,17], among others.…”

Section: Introductionmentioning

confidence: 99%

Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

et al. 2021

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In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.

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“…In this way, a single HRS and multiple LRS (corresponding to different compliance currents) are implemented and, the physical phenomenon is believed to be the formation and subsequent widening of the conductive filament with increasing compliance current ( Fig.1-(a)). Demonstration of MLC in RRAM by varying the compliance current can be found in [6]- [9] (read-out currents of some of these MLC RRAMs is listed in Table I).…”

Section: Introductionmentioning

confidence: 99%

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Reuben

Fey

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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The quest to increase memory density in Resistive Random Access Memory (RRAM) has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. Implementing multiple states narrows the distance between states, making sensing of MLC RRAM a challenging task. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The circuit distinguishes between the states by the relative current's magnitude and hence does not require an absolute reference. Simulations in IHP's 130 nm CMOS technology confirmed fast (single step) sensing while tolerating appropriate variations in the sensed resistance. The proposed circuit is also area efficient when compared to conventional parallel sensing approach.

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Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention

Cited by 56 publications

References 36 publications

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

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