A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

Bonato, Vanderlei; Marques, Eduardo; Constantinides, George A.

doi:10.1109/tcsvt.2008.2004936

Cited by 158 publications

(140 citation statements)

References 15 publications

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“…To speed up the SIFT operation, a number of previous research efforts have been made [3][4][5]. Among them, one presents a hardware-based implementation that achieves a real-time SIFT operation of QVGA-sized (320x240) video at the rate of 30 frames per second [1]. Although this work in [1] enables a real-time SIFT operation, the hardware cost is very large because intermediate results are stored in internal memory inside a chip.…”

Section: Introductionmentioning

confidence: 99%

“…Among them, one presents a hardware-based implementation that achieves a real-time SIFT operation of QVGA-sized (320x240) video at the rate of 30 frames per second [1]. Although this work in [1] enables a real-time SIFT operation, the hardware cost is very large because intermediate results are stored in internal memory inside a chip. In a PC environment, it is an efficient approach to speed up the computation with an increased memory requirement because a PC has sufficient memory but a limited computing power for SIFT computation.…”

Section: Introductionmentioning

confidence: 99%

“…As a result, the buffer size to store the input image is also reduced because only the partitioned sub-image needs to be stored in the buffer. The entire procedure for the SIFT computation is implemented in hardware and the computation speed is increased by about 30 times when compared with the previous work [1].…”

Section: Introductionmentioning

confidence: 99%

“…Previous work on hardwarebased SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work.…”

mentioning

confidence: 99%

“…As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.…”

mentioning

confidence: 99%

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A novel hardware design for SIFT generation with reduced memory requirement

Kim¹,

Lee²

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardwarebased SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A novel hardware design for SIFT generation with reduced memory requirement

Kim¹,

Lee²

2013

JSTS:Journal of Semiconductor Technology and Science

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An all‐hardware implementation of the subpixel refinement stage in SIFT algorithm

Rubio‐Ibáñez

Ruiz‐Merino

Doménech‐Asensi

et al. 2018

Circuit Theory & Apps

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This paper proposes an all-hardware architecture to perform the subpixel refinement operation in the scale invariant transform algorithm. Although the literature describes several hardware implementations of this algorithm, due to its complexity, most of them are based on simplifications of it. These implementations normally exclude the subpixel refinement stage, which, however, is an essential process to obtain accurate results in image matching applications.The architecture has been described in very high-speed integrated circuit hardware description language at register transfer level and synthesized on a Xilinx Zynq 7020 device. The latency of the proposed architecture to generate a refinement operation is 211 clock cycles, and the throughput achieved exploiting pipeline techniques is 64 cycles. The architecture uses fixed-point data representation and has been tested with images from known databases, yielding very good performance compared with the floating-point software implementation of the algorithm.

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Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering

Lopez

Napoli

Strollo

2015

Lecture Notes in Electrical Engineering

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The Scale Invariant Feature Transform (SIFT) extracts relevant features from images and video frames. The extracted features are robust against luminance variations, geometrical transformations, and image resolution. Due to its performances, the SIFT algorithm is of great importance in fields such as object recognition, content retrieval from image databases, robotic navigation, and gesture recognition. Main drawback of the SIFT algorithm is the high computational complexity. This paper presents the development of a hardware filtering accelerator for the implementation of SIFT-based visual search. The accelerator works in the frequency domain, operating on a block-by-block basis. This enables to work faithfully to the original Scale-Space theory, which employes non-separable Laplacian of Gaussian (LoG) filters. The targeted throughput is of ∼20 fps, making the coprocessor suitable for real time processing.

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A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

Cited by 158 publications

References 15 publications

A novel hardware design for SIFT generation with reduced memory requirement

A novel hardware design for SIFT generation with reduced memory requirement

An all‐hardware implementation of the subpixel refinement stage in SIFT algorithm

Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering

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