A novel hardware design for SIFT generation with reduced memory requirement

Kim, Eung Sup; Lee, Hyuk-Jae

doi:10.5573/jsts.2013.13.2.157

Cited by 20 publications

(2 citation statements)

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“…Since a large amount of computation is required in a SIFT algorithm, optimized hardware accelerators for SIFT have been proposed [3][4][5][6][7]. The ASIFT algorithm generates many images transformed by affine transforms in order to simulate the view change of a camera.…”

Section: Introductionmentioning

confidence: 99%

Fast Execution of an ASIFT Hardware Accelerator by Prior Data Processing

2019

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This paper proposes a new ASIFT hardware architecture that processes a Video Graphics Array (VGA)-sized (640 × 480) video in real time. The previous ASIFT accelerator suffers from low utilization because affine transformed images are computed repeatedly. In order to improve hardware utilization, the proposed hardware architecture adopts two schemes to increase the utilization of a bottleneck hardware module. The first is a prior anti-aliasing scheme, and the second is a prior down-scaling scheme. In the proposed method, 1 × 1 and 0.5 × 1 blurred images are generated and they are reused for creating various affine transformed images. Thanks to the proposed schemes, the utilization drop by waiting for the affine transform is significantly decreased, and consequently, the operation speed is increased substantially. Experimental results show that the proposed ASIFT hardware accelerator processes a VGA-sized video at the speed of 28 frames/s, which is 1.36 times faster than that of previous work. and stores it in an external memory. By reusing the stored image for generating various simulated images, redundant data fetching for generating the 1 × 1 blurred image is removed. The second is a prior down-scaling scheme. A 0.5 × 1 blurred image is generated and reused for generating the simulated images of which the width is scaled less than 0.5 times. A word of the 0.5 × 1 blurred image includes more valid pixels than that of the 1 × 1 blurred image. Thus, the stall cycles to wait for valid data are decreased. As a result, the proposed ASIFT hardware implementation processes a VGA-sized video at 28 fps. Previous Work ASIFT AlgorithmAn ASIFT algorithm is proposed to achieve full affine invariance such that it can find correspondences in two images representing the same scene even though they are obtained from any viewpoints [2]. In an ASIFT algorithm, simulated images for various camera viewpoints are generated by transforming a source image with affine transform matrices. Then, SIFT features are computed in the simulated images. Because these SIFT features are obtained by considering the viewpoint change, correspondences can be found between two images for which the camera viewpoints are different.The images captured by a camera at various positions can be interpreted as affine decomposition. The camera position is represented on hemispherical coordinates as shown in Figure 1. The center (o) of the hemisphere is located at the center of a source image u. The latitude and longitude of the position of the camera are represented by θ and ϕ, respectively. The affine distortion caused by the change of the camera position is interpreted as the rotation and scaling of an image. The affine transform is represented by Equation (1). In this equation, image rotation and scaling are represented by a rotation matrix (R ϕ ) and a scaling matrix (T 1,1/t ), respectively. A = T 1,1/t R ϕ = 1 0 0 1/t

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Section: Introductionmentioning

confidence: 99%

Fast Execution of an ASIFT Hardware Accelerator by Prior Data Processing

2019

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“…Meanwhile, very few studies have been conducted to optimize the arithmetic units and improve their performances. Other simplifications of the above-cited methods regard reductions of the algorithm's complexity, such as the reduction in the number of scales or octaves or a decrease of the value of the standard deviation of the Gaussian filter in the case of SIFT applications [13,14].…”

Section: Introductionmentioning

confidence: 99%

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

2017

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Exploiting the Bachet weight decomposition theorem, a new two-dimensional filter is designed. The filter can be adapted to different multimedia applications, but in this work it is specifically targeted to image processing applications. The method allows emulating standard 32 bit floating point multipliers using a chain of fixed point adders and a logic unit to manage the exponent, in order to obtain IEEE-754 compliant results. The proposed design allows more compact implementation of a floating point filtering architecture when a fixed set of coefficients and a fixed range of input values are used. The elaboration of the data proceeds in raster-scan order and is capable of directly processing the data coming from the acquisition source thanks to a careful organization of the memories, avoiding the implementation of frame buffers or any aligning circuitry. The proposed architecture shows state-of-the-art performances in terms of critical path delay, obtaining a critical path delay of 4.7 ns when implemented on a Xilinx Virtex 7 FPGA board

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Enhancing Gadgets for Blinds Through Scale Invariant Feature Transform

Kumar

Wiil

2019

Recent Advances in Computational Intelligence

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The series "Studies in Computational Intelligence" (SCI) publishes new developments and advances in the various areas of computational intelligence-quickly and with a high quality. The intent is to cover the theory, applications, and design methods of computational intelligence, as embedded in the fields of engineering, computer science, physics and life sciences, as well as the methodologies behind them. The series contains monographs, lecture notes and edited volumes in computational intelligence spanning the areas of neural networks, connectionist systems, genetic algorithms, evolutionary computation, artificial intelligence, cellular automata, self-organizing systems, soft computing, fuzzy systems, and hybrid intelligent systems. Of particular value to both the contributors and the readership are the short publication timeframe and the world-wide distribution, which enable both wide and rapid dissemination of research output.The books of this series are submitted to indexing to Web of Science, EI-Compendex, DBLP, SCOPUS, Google Scholar and Springerlink.

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A novel hardware design for SIFT generation with reduced memory requirement

Cited by 20 publications

References 6 publications

Fast Execution of an ASIFT Hardware Accelerator by Prior Data Processing

Fast Execution of an ASIFT Hardware Accelerator by Prior Data Processing

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

Enhancing Gadgets for Blinds Through Scale Invariant Feature Transform

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