A new analytical model of 4H-SiC DMOSFETs that is useful to explore their thermal stability is presented. The model is capable to describe, with closed form equations, the DC forward behavior of devices in a wide temperature range, including the effects of parasitic resistances and oxide interface traps. The model allows to analyze the on-set of electro-thermal stability of 4H-SiC DMOSFETs both in triode and in saturation region, and to monitor the impact of the series resistance and traps on reliable operation of devices. The accuracy of the model has been verified by comparisons with numerical simulations that evidence the effect of trap densities in the range [0-1014] cm-2eV-1 for operating temperatures up to 500K. Comparisons with experimental data of 1.2kV and 1.7kV commercial devices are used to validate the model

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A new analytical description of the trapped charge\ud distribution at the semiconductor–insulator interface of 4H-SiC\ud vertical-DMOSFET has been derived as a function of the surface\ud potential into the channel. The model allows one to accurately\ud calculate the electrical characteristics of the device in both\ud subthreshold and above-threshold operations, namely, when the\ud channel works from weak accumulation to strong inversion. The\ud accuracy of the model has been verified by comparisons with\ud numerical simulations and with experimental measurements of\ud a 1.7-kV commercial device

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