A parallel hardware architecture for connected component labeling based on fast label merging

Flatt, Holger; Blume, S.; Hesselbarth, Sebastian; Schunemann, T.; Pirsch, P.

doi:10.1109/asap.2008.4580169

Cited by 22 publications

(8 citation statements)

References 9 publications

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“…There are a variety of algorithms for this task. For example, there are a number of different parallel approaches [7,18], some methods using specialized hardware [5,9], and some using GPU-type accelerators [8]. In our application, the image sizes are relatively modest.…”

Section: Feature Detection On Mesh Datamentioning

confidence: 98%

Detecting atmospheric rivers in large climate datasets

Byna

Prabhat

Wehner

et al. 2011

Proceedings of the 2nd International Workshop on Petascal Data Analytics: Challenges and Opportunities

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Extreme precipitation events on the western coast of North America are often traced to an unusual weather phenomenon known as atmospheric rivers. Although these storms may provide a significant fraction of the total water to the highly managed western US hydrological system, the resulting intense weather poses severe risks to the human and natural infrastructure through severe flooding and wind damage. To aid the understanding of this phenomenon, we have developed an efficient detection algorithm suitable for analyzing large amounts of data. In addition to detecting actual events in the recent observed historical record, this detection algorithm can be applied to global climate model output providing a new model validation methodology. Comparing the statistical behavior of simulated atmospheric river events in models to observations will enhance confidence in projections of future extreme storms.Our detection algorithm is based on a thresholding condition on the total column integrated water vapor established by Ralph et al. (2004) followed by a connected component labeling procedure to group the mesh points into connected regions in space. We develop an efficient parallel implementation of the algorithm and demonstrate good weak and strong scaling. We process a 30-year simulation output on 10,000 cores in under 3 seconds.

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Section: Feature Detection On Mesh Datamentioning

confidence: 98%

Detecting atmospheric rivers in large climate datasets

Byna

Prabhat

Wehner

et al. 2011

Proceedings of the 2nd International Workshop on Petascal Data Analytics: Challenges and Opportunities

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“…The latter has the same size of the input image and contains the labels assigned to the input pixels.Several attempts to improve the performance of these algorithms were presented in the recent past. They exploit parallelism by means of either multi-core processors and Graphics Processing Units (GPUs) [5,[27][28][29][30][31] or custom hardware architectures [10,11,[14][15][16][17][18][19][20][21][22][23]26]. As it is well known, for many consumer applications, like those related to the Internet of things (IoT), reaching high speed is as important as achieving low cost and high energy efficiency [16,32].…”

mentioning

confidence: 99%

“…Both input and output data bandwidths are kept limited and both read and write accesses on the image memory are maintained regularly. The proposed design complies with the fourth generation of the high-performance advanced extensible interface (AXI4) protocol [33], and, differently from several existing hardware accelerators designed as standalone modules [23,[29][30][31], time and resource overheads required to comply with the communication protocol are taken into account.For purposes of comparison with existing competitors, different implementation platforms were used. Speed performances and resources requirements of the novel parallel hardware design were analyzed for image sizes ranging from 640 × 480 to 2k × 2k with the number of manageable labels varying between 64 and 8192.…”

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confidence: 99%

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confidence: 99%

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A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

2020

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Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory.

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“…Component labeling assigns a unique label to each connected component in an image. The classical 2-pass labeling of an image component is described in [7] and is shown in Figure 2. The pixel neighborhood is analyzed for the 8-connectivity.…”

Section: Introductionmentioning

confidence: 99%

Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA

Malik

Thörnberg

Imran

et al. 2014

International Journal of Distributed Sensor Networks

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This paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine vision systems demand a robust performance and power efficiency as well as minimum area utilization, depending on the deployed application. In the proposed architecture, the hardware modules for component labeling and feature calculation run in parallel. A CMOS image sensor (MT9V032), operating at a maximum clock frequency of 27 MHz, was used to capture the images. The architecture was synthesized and implemented on a Xilinx Spartan-6 FPGA. The developed architecture is capable of processing 390 video frames per second of size 640 × 480 pixels. Dynamic power consumption is 13 mW at 86 frames per second.

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A parallel hardware architecture for connected component labeling based on fast label merging

Cited by 22 publications

References 9 publications

Detecting atmospheric rivers in large climate datasets

Detecting atmospheric rivers in large climate datasets

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA

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