A parallel spiking neural network simulator

Cheung, Kit; Schultz, Simon R.; Leong, Philip H. W.

doi:10.1109/fpt.2009.5377667

Cited by 19 publications

(10 citation statements)

References 11 publications

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“…And also it implies an approximation of the spike timestamp as high as the pipeline extension. We suppose that such an approximation do not interfere with their applications [1,4,6,10,11], but the same cannot be said to all applications.…”

Section: Resultsmentioning

confidence: 99%

Low Latency FPGA Implementation of Izhikevich-Neuron Model

Bandeira

Costa

Bontorin

et al. 2017

System Level Design From HW/SW to Memory for Embedded Systems

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The Izhikevich's simple model (ISM) for neural activity presents a good compromise between waveform quality and computational cost. FPGAs (Field Programmable Gate Array) are powerful, flexible, and inexpensive digital hardware that can implement such model. In this paper, we present a highly combinational, low latency implementation of ISM for FPGA. In the absence of official benchmark to compare different implementations, we propose two different metrics to compare the technical literature with our implementation. In this benchmark, we can implement a system that, when compared to the literature, has almost 1.5 times the number of digital neurons (DN), and latency more than 56 times smaller. This shows that our implementation is best suited for hybrid network systems and presents a fair performance for only-artificial networks.

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Section: Resultsmentioning

confidence: 99%

Low Latency FPGA Implementation of Izhikevich-Neuron Model

Bandeira

Costa

Bontorin

et al. 2017

System Level Design From HW/SW to Memory for Embedded Systems

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“…This optimization is based on the fact that new neuron states do not need to be calculated at every single time step but only in the instances that a new input arrives at the neuron, as otherwise the neuron state would not change. To improve on their initial memory-bandwidth requirements [4], Cheung et al replaced the FPGA board with a Maxeler Dataflow Machine [5]. This FPGA-based device features state-of-the-art memory systems that increase the bandwidth capabilities greatly compared to simple FPGA boards.…”

Section: Related Workmentioning

confidence: 98%

“…Two of the most notable implementations using Izhikevich neurons are the designs proposed by Cheung et al [5,4] and by Moore et al (Bluehive [15]). Each approach proposed an FPGA architecture for very large-scale SNNs which is event-driven for optimizing the network traffic and the assorted memory-bandwidth needs.…”

Section: Related Workmentioning

confidence: 98%

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

Smaragdos

Isaza

Eijk

et al. 2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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The Inferior-Olivary nucleus (ION) is a well-charted region of the brain, heavily associated with sensorimotor control of the body. It comprises ION cells with unique properties which facilitate sensory processing and motor-learning skills. Various simulation models of ION-cell networks have been written in an attempt to unravel their mysteries. However, simulations become rapidly intractable when biophysically plausible models and meaningful network sizes (≥100 cells) are modeled. To overcome this problem, in this work we port a highly detailed ION cell network model, originally coded in Matlab, onto an FPGA chip. It was first converted to ANSI C code and extensively profiled. It was, then, translated to HLS C code for the Xilinx Vivado toolflow and various algorithmic and arithmetic optimizations were applied. The design was implemented in a Virtex 7 (XC7VX485T) device and can simulate a 96-cell network at real-time speed, yielding a speedup of ×700 compared to the original Matlab code and ×12.5 compared to the reference C implementation running on a Intel Xeon 2.66GHz machine with 20GB RAM. For a 1,056-cell network (non-real-time), an FPGA speedup of ×45 against the C code can be achieved, demonstrating the design's usefulness in accelerating neuroscience research. Limited by the available on-chip memory, the FPGA can maximally support a 14,400-cell network (non-real-time) with online parameter configurability for cell state and network size. The maximum throughput of the FPGA IONnetwork accelerator can reach 2.13 GFLOPS.

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“…[K. Cheung et al 2009] and [M. Ambroise et al 2013] choose to design their networks using a register transfer level (RTL) language such as VHDL. Although this has the benefit of fine control over the implementations details, it significantly reduces the overall design productivity compared with a higher-level abstraction flow.…”

Section: Related Workmentioning

confidence: 99%

“…Storage and memory resource optimization are essential considerations and often the aim is to maximize their utilization. That is the case in [K. Cheung et al 2009] that uses 18-bit and 9-bit two's complement precision to fully utilise the 18-bit two's complement multipliers of the DSP blocks available in the FPGA device. Another example is driven by memory availability; in this case [D. Thomas et al 2009] stores four synaptic weights of 9 bits in one 36-bit register in internal BRAM to maximize BRAM utilization using C as the high-level design language.…”

Section: Related Workmentioning

confidence: 99%

Energy proportional streaming spiking neural network in a reconfigurable system

Sanchez

Nunez-Yanez²

2017

Microprocessors and Microsystems

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This paper presents a high-performance architecture for spiking neural networks that optimizes data precision and streaming of configuration data stored in main memory. The neural network is based on the Izhikevich model and mapped to a CPU-FPGA hybrid device using a high-level synthesis flow. The active area of the network is configurable and this feature is used to create an energy proportional system. Voltage and frequency scaling are applied to the processing hardware and memory system to deliver enough processing and memory bandwidth to maintain real-time performance at minimum power and energy levels. The experiments show that the application of voltage and frequency scaling to DDR memory and programmable logic can reduce its energy requirements by up to 77% and 76% respectively. The performance evaluation show that the solution is superior to competing high-performance hardware, while voltage and frequency scaling reduces overall energy requirements to less than 2% of a software-only implementation at the same level of performance. Index terms: Hardware → Integrated circuits → Reconfigurable logic and FPGAs → Hardware accelerators, Hardware → Integrated circuits → Reconfigurable logic and FPGAs → Reconfigurable logic applications

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A parallel spiking neural network simulator

Cited by 19 publications

References 11 publications

Low Latency FPGA Implementation of Izhikevich-Neuron Model

Low Latency FPGA Implementation of Izhikevich-Neuron Model

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

Energy proportional streaming spiking neural network in a reconfigurable system

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