A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors

Yeo, Kyongmin; Oh, Chang Woo; Kim, Sung Min; Kim, Min Sang; Lee, Chang Sub; Lee, Sung Young; Han, Sangyong; Yoon, Eunchul; Cho, Hye Jin; Lee, Doo Youl; Yoon, Byung Moon; Rhee, Hwa Sung; Lee, Byung Chan; Choe, Jeong-Dong; Chung, Ilsub; Park, Donggun; Kim, Kinam

doi:10.1109/led.2004.830064

Cited by 30 publications

(12 citation statements)

References 11 publications

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“…Fortunately, the high-k gate dielectrics can be used to meet the stringent J g,limit for high-performance applications. A PUC process 8) used for forming the SDT structure and the fin pattern formation 9,10) are two key process steps for the SDT FinFET. This paper presents another type of FinFETs, which shows how SDT can be easily added to conventional FinFETs for reducing both SCEs and SHE at the same time for low-cost, high-performance applications at deca-nanoscale regime.…”

Section: Performance Prediction Of Sdt Dg-finfetsmentioning

confidence: 99%

“…This paper presents a simple method of fabricating a new source/drain (S/D)-tied (SDT) DG-FinFET through existing techniques [6][7][8][9][10] and applies device simulation to investigate its dc and RF/analog properties comprehensively. Besides the investigation of fin width (W fin ) variation in SDT FinFETs, the body-tied (BT) and silicon-on-insulator (SOI) FinFETs were also designed for performance comparison.…”

Section: Introductionmentioning

confidence: 99%

“…According to the simulations, the SDT FinFET shows better scalability than the BT FinFET (BT: 127 mV/V at 90 mV/dec and SDT: 123 mV/V at 79 mV/dec) and exhibits negligible self-heating effects (SHE), which is a difficult task for an SOI FinFET (SOI: ÁI d =I d,w=oSHE % 2:3% and SDT: ÁI d =I d,w=oSHE % 0:37%). These two advantages are due to the combined application of partially insulating oxide (PiOX) under channel (PUC) 8) and SDT in the proposed FinFET. A comparison was also done between SDT FinFET and the existing experimental data.…”

Section: Introductionmentioning

confidence: 99%

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A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

Eng¹,

Lin²,

Chang³

et al. 2011

Jpn. J. Appl. Phys.

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This paper presents a three-dimensional (3D) simulation study of source/drain (S/D)-tied (SDT) double-gate (DG) fin field-effect transistor (FinFET) design for 16-nm half-pitch technology generation and beyond using technology computer-aided design (TCAD) tools. A simple process to fabricate the proposed SDT FinFET is proposed. An investigation of the fin width (W fin) on the electrical characteristics is shown, suggesting that a reduced W fin is good for both the suppression of short-channel effects and the reduction of parasitic capacitance in SDT FinFETs. Also, the self-heating can be well controlled in our proposed SDT FinFET which is a difficult task for SOI family. The proposed FinFET is also compared with the existing experimental data, showing that the SDT FinFET not only demonstrates desired short-channel characteristics due to its inherent structure advantages (partially insulating oxide under the channel region), but also reduces the costs of device fabrication due to its simple process method and planar-like structure.

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Section: Performance Prediction Of Sdt Dg-finfetsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

Eng¹,

Lin²,

Chang³

et al. 2011

Jpn. J. Appl. Phys.

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“…2 shows the proposed process flow for fabricating the novel Pi-OXJLT structure. A similar process flow has also been used in [18], [19][20]. The starting material is silicon with p-type doping (see Fig.…”

Section: Introductionmentioning

confidence: 99%

A novel partially insulated junctionless transistor for low power nanoscale digital integrated circuits

Patil

Bonge

Malode

et al. 2014

2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)

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In this paper, a novel device structure named as partially insulated (Pi-OX) junctionless transistor (JLT) is proposed and the simulated results below 20 nm have been compared with existing silicon-on-insulator (SOI) JLT. Further, drain-induced barrier lowering (DIBL), subthreshold swing (SS), on-state drive current (I ON ), off-state leakage current (I OFF ), I ON /I OFF ratio and static power dissipation (P STAT ) of the proposed Pi-OXJLT and SOIJLT has also been compared. It has been found that, I OFF, DIBL and SS in the case of proposed Pi-OXJLT are reduced by 57%, 17% and 10% respectively over the existing SOIJLT device. The fabrication flow of the proposed Pi-OXJLT is proposed.

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“…To the best of our knowledge, this is the first time that a circuit analysis for a plasma based device BCPT and the proposed SELBOX-BCPT has been performed. Further, a process flow for the fabrication of the proposed device, employing SiGe removal technique to create the partial buried oxide has also been proposed for fabricating the proposed device [24,27].…”

Section: Introductionmentioning

confidence: 99%

A high performance charge plasma based lateral bipolar transistor on selective buried oxide

Loan¹,

Bashir²,

Rafat³

et al. 2013

Semicond. Sci. Technol.

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In this paper, we present a new structure of lateral bipolar transistor on selective buried oxide. The device does not use highly doped regions; however, it employs the concept of creating n and p type charge plasma in undoped silicon by using metal electrodes of different work functions. The proposed device is named as the selective buried oxide based bipolar charge plasma transistor (SELBOX-BCPT). An extensive 2D simulation study has revealed that the proposed SELBOX-BCPT device not only possesses all the advantages of the conventional BCPT device, but it also addresses various severe problems of the BCPT device. A significant improvement in major issues of poor cutoff frequency ( f T ), low breakdown voltage and thermal efficiency has been achieved. It has been observed that the f T has increased by ∼94.6%, the breakdown voltage by 23.47% and the device is much cooler than the conventional BCPT device. A large current gain is obtained in the proposed device and is on a par with the conventional BCPT device. Further, by using mixed-mode simulation feature of the Atlas simulator, inverting amplifiers based on SELBOX-BCPT and the conventional BCPT have been realized. A significant improvement of 15% in switching-on transient time and 25.8% in switching-off transient time has been achieved in the proposed device in comparison to the conventional BCPT device.

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A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors

Cited by 30 publications

References 11 publications

A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

A novel partially insulated junctionless transistor for low power nanoscale digital integrated circuits

A high performance charge plasma based lateral bipolar transistor on selective buried oxide

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