Recent developments in complimentary metal–oxide semiconductor (CMOS)‐driven compound semiconductors (III–V), Germanium (Ge) and two‐dimensional (2‐D) materials technologies provide new opportunities in advancing the performance envelope of MOS device as well as the relevant electrical characterization techniques. Understanding the electrical characteristics of the metal–oxide–semiconductor (MOS) interface and defects through capacitance‐voltage (CV), conductance voltage (GV) and ac‐transconductance responses can lead to more realistic assessments of the oxide–semiconductor material systems and accurate performance predictions. In this article, interface trap density distributions
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) of Germanium, III–V compound semiconductors are characterized and/or illustrated. The characterization, modeling and temperature dependence of oxide border traps are presented as the defect study probes beyond the oxide–semiconductor interface. Finally, an investigation on 2‐D materials based MOS devices extends the ac admittance techniques beyond conventional semiconductor materials.