A placement strategy for reducing the effects of multiple faults in digital circuits

Pagliarini, Samuel; Pradhan, Dhiraj K.

doi:10.1109/iolts.2014.6873674

Cited by 9 publications

(5 citation statements)

References 10 publications

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“…For METs (or MUBs), in [24], via calculation of pass/fail value for all possible pairs of the circuit, all pairs are decomposed into two sets: good pairs and bad pairs. A simulated annealing-based optimization is then accomplished for maximizing the elements of good pairs set.…”

Section: Related Workmentioning

confidence: 99%

“…1) Most of them only consider SETs ( [23], [25], [26]) or METs ( [24], [27]) and do not cover all transient faults originated by both SETs and METs. It should be noted that most of the methods proposed for hardening against METs cannot be simplified to handle SETs because having multiple error sites and using their interactions is their main assumption.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs

Kiarash¹,

Pedram²,

Ghavami³

et al. 2021

Preprint

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Nowadays nanoscale combinational circuits are facing significant reliability challenges including soft errors and process variations. This paper presents novel process variation-aware placement strategies that include two algorithms to increase the reliability of combinational circuits against both Single Event Transients (SETs) and Multiple Event Transients (METs). The first proposed algorithm is a global placement method (called SeaPlace-G) that places the cells for hardening the circuit against SETs by solving a quadratic formulation. Afterwards, a detailed placement algorithm (named SeaPlace-D) is proposed to increase the circuit reliability against METs by solving a linear programming optimization problem. Experimental results show that SeaPlace-G and SeaPlace-D averagely achieve 41.78% and 32.04% soft error reliability improvement against SET and MET, respectively. Moreover, when SeaPlace-D is followed by SeaPlace-G, MET reduction can be improved by up to 53.3%.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs

Kiarash¹,

Pedram²,

Ghavami³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Modifying compiler-generated placement has the potential for masking SEMT-induced errors (Ebrahimi et al 2016) without cost to chip area, but without a charge sharing model based on shared wells in a placed and routed (P&R) IC, the benefits of this post-EDA placement are not clear. Alternatively, creating a new, reliability-focused placement algorithm could mask errors even further (Pagliarini and Pradhan 2014), again from a simple model excluding charge sharing, but at the high cost of 2x or more wirelength, design timing, and dynamic power draw.…”

Section: Motivation and Related Workmentioning

confidence: 99%

Relative logic cell placement for mitigation of charge sharing-induced transients

Kiddie¹,

Robinson²

2016

Semicond. Sci. Technol.

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Design of modern integrated circuits increasingly requires consideration of radiation effects, especially in space and other high-risk environments. With fabrication technologies scaling down both feature sizes and critical charge, a radiation strike in sub-100 nm technologies may affect multiple, physically adjacent nodes. With increasing clock speeds, transient errors in the processing datapath also increase in risk. Modeling single-event multiple-transients (SEMT) for pre-fabrication reliability characterization has become a more common design step, and this work adds to the state-of-the-art by providing a fast and physically-informed characterization flow that captures the effects of single-event multiple-node charge collection through experimentally observed transport mechanisms. Beyond characterization, the study of SEMT vulnerabilities reveals the electronic design automation (EDA) step of standard logic cell placement as a design space for hardening against SEMT-induced errors. This work: (1) analyzes the vulnerability of benchmark circuits against SEMT errors, (2) evaluates the impact of logic on transient propagation, (3) explores EDA placement techniques, and (4) builds an automated design flow for relative placement of cells to mask transient errors, while maintaining compatibility with other radiation hardening techniques. Zero cost to area and marginal impact on timing enable this new cell placement algorithm that masks 30% of SEMT-induced errors.

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“…For instance, in [15], a careful analysis of the effect of placement with respect to multiple faults was performed. A placement engine that is fault-aware is proposed in [16], albeit presenting heavy overheads. An improved version is presented in [17].…”

Section: Introductionmentioning

confidence: 99%

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

Pagliarini

Benites

Martins

et al. 2021

IEEE Trans. Nucl. Sci.

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In this paper, authors explore radiation hardening techniques through the design of a test chip implemented in 16 nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multiplication were taped-out and irradiated with neutrons. The results obtained from the neutron campaign revealed that the radiation hardened variants present superior resiliency when either local or global TMR schemes are employed. Furthermore, simulation-based fault injection was utilized to validate the measurements and to explore the effects of different implementation strategies on failure rates. We further show that the interplay between these different implementation strategies is not trivial to capture and that synthesis optimizations can effectively break assumptions about the effectiveness of redundancy schemes.

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A placement strategy for reducing the effects of multiple faults in digital circuits

Cited by 9 publications

References 10 publications

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs

Relative logic cell placement for mitigation of charge sharing-induced transients

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

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