Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

Abstract

In this paper, authors explore radiation hardening techniques through the design of a test chip implemented in 16 nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multiplication were taped-out and irradiated with neutrons. The results obtained from the neutron campaign revealed that the radiation hardened variants present superior resiliency when either local or global TMR schemes are employed. Furthermore, simulation-based fault injection was utilized to validate the measurements and to explore the effects of different implementation strategies on failure rates. We further show that the interplay between these different implementation strategies is not trivial to capture and that synthesis optimizations can effectively break assumptions about the effectiveness of redundancy schemes.

A Survey on Dynamic Corrective Control of Asynchronous Sequential Machines

“…To this end, previous research on network attacks in cyber-physical systems (CPSs) [114][115][116] must be incorporated into corrective control theory. (ii) Though many convincing experimental evaluations of corrective controllers exist, there is still a lack of application studies which validate that asynchronous digital systems embedded with the corrective controller show fault-hardening ability [117][118][119] against real radiation-related faults. For this purpose, radiation exposure experiments [120] on the implemented corrective control systems must be conducted.…”

Obfuscating the Hierarchy of a Digital IP

“…There are many parameters and options to define/select when performing logic synthesis, so it ought to be studied if the chosen options indeed generate different netlists. Based on the findings of [8], we apply the following optimization techniques:…”