A platform for secure IP integration in Xilinx Virtex FPGAs

Abstract

Advancements in silicon, software and IP support have made Field Programmable Gate Arrays (FPGAs) a highly flexible solution for many applications. With the growing number of companies providing IP support for FPGAs, IP license violations by over-deployment of IP into more devices than originally licensed remains a major concern for IP owners. In this paper we present a solution for secure IP exchange and configuration based on the Dynamic Partial Reconfiguration (DPR) feature in Xilinx FPGAs. Our system deploys DPR to integrate encrypted hard-macro IP cores into identifiable FPGA devices. These IP cores are configured using a proposed partial bitstream relocation technique to allow for a flexible design flow. We present a proof-of-concept implementation of a secure internal reconfiguration engine on a Xilinx Virtex-6 FPGA.