Achieving efficient spatial modulation of phonon transmission is an essential step on the path to phononic circuits using "phonon currents". With their intrinsic and reconfigurable interfaces, domain walls (DWs), ferroelectrics are alluring candidates to be harnessed as dynamic heat modulators. This paper reports the thermal conductivity of single-crystal PbTiO 3 thin films over a wide variety of epitaxial-strain-engineered ferroelectric domain configurations. The phonon transport is proved to be strongly affected by the density and type of DWs, achieving a 61% reduction of the room-temperature thermal conductivity compared to the single-domain scenario. The thermal resistance across the ferroelectric DWs is obtained, revealing a very high value (≈5.0 × 10 −9 K m 2 W −1 ), comparable to grain boundaries in oxides, explaining the strong modulation of the thermal conductivity in PbTiO 3 . This low thermal conductance of the DWs is ascribed to the structural mismatch and polarization gradient found between the different types of domains in the PbTiO 3 films, resulting in a structural inhomogeneity that extends several unit cells around the DWs. These findings demonstrate the potential of ferroelectric DWs as efficient regulators of heat flow in one single material, overcoming the complexity of multilayers systems and the uncontrolled distribution of grain boundaries, paving the way for applications in phononics.

In nanometer technology regime, design components mandate their reuse to meet the complex design challenges and hence comprise Intellectual Property (IP). Unauthorized reuse raises major security issues. IP mark(s) is embedded into a design for establishing the veracity of a legal IP owner/buyer. However, methods for trustworthy public verification of IP marks are not secure. For field-programmable gate-array (FPGA) designs, marks become prone to tampering, and even being overridden by an attacker's signature after public verification. In order to ensure trustworthy yet leakage-proof public verification based on the marks hidden in a FPGA design, we propose a zero-knowledge protocol Verify_ZKP. It is an interactive two-person game between the prover and the verifier. This protocol is fast, incurs no additional design overhead, and needs no centralized signature database. We establish that Verify_ZKP satisfies zero-knowledge property, and introduce statistical metrics to measure its robustness. We have simulated our protocol for IWLS'05 FPGA benchmarks. Experimental results on robustness and overhead are very encouraging.Index Terms-Design-for-security, VLSI field-programmable gate-array (FPGA) design, watermark verification, zero-knowledge protocol.

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