A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization

Sidiropoulos, Harry; Figuli, Peter; Siozios, Kostas; Soudris, Dimitrios; Becker, J.

doi:10.1109/fpl.2013.6645564

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…use cases: First, as an abstraction layer, providing a common bitstream format independent of commercial FPGA architectures. This allows using features such as partial dynamic reconfiguration on FPGAs which do not natively support this [6]. Secondly, V-FPGAs can be used for FPGA architecture research: Novel ideas can be integrated in the architecture and tested on a hardware implementation, which can provide additional insight compared to simulation.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA

Pfau¹,

Zaki

Becker³

2021

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Virtual FPGA (V-FPGA) architectures are useful as both early prototyping testbeds for custom FPGA architectures, as well as to enable advanced features which may not be available on a given host FPGA. V-FPGAs use standard FPGA synthesis and placement tools, and as a result the maximum application frequency is largely determined by the synthesis of the V-FPGA onto the host FPGA. Minimal net delays in the virtual layer are crucial for applications, but due to increased routing congestion, these delays are often significantly worse for larger than for smaller designs. To counter this effect, we investigate three different placement strategies with varying amounts of manual intervention. Taking the regularity of the V-FPGA architecture into account, a regular placement of tiles can lead to an 37 % improvement in the achievable clock frequency. In addition, uniformity of the measured net delays is increased by 39 %, which makes implementation of user applications more reproducible. As a trade-off, these manual placement strategies increase area usage of the virtual layer up to 16 %.

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Section: Introductionmentioning

confidence: 99%

Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA

Pfau¹,

Zaki

Becker³

2021

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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“…The work of [Huang 2009] virtualizes hardware components in HW-SW designs. Another approach targets the virtualization of whole FPGAs [Figuli 2011, Sidiropoulos 2013. Task switching procedures for hardware tasks were proposed, e. g., in , Jozwik 2012, with the last one explicitly targeting virtualization features.…”

Section: The Term Virtualizationmentioning

confidence: 99%

Design Concepts for a Virtualizable Embedded MPSoC Architecture

Biedermann¹

2014

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“…V-FPGA architectures have been applied for three main use cases: First, as an abstraction layer, providing a common bitstream format independent of commercial FPGA architectures. This allows using features such as partial dynamic reconfiguration on FPGAs which do not natively support this [2]. Second, V-FPGAs can be used for FPGA architecture research: Novel ideas can be integrated in the architecture and tested on a hardware implementation, which can provide additional insight compared to simulation.…”

Section: Introductionmentioning

confidence: 99%

V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling

Pfau¹,

Zaki

Becker³

2022

J Sign Process Syst

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Virtual FPGAs (V-FPGAs) are used as vendor-independent virtualization layers, to retrofit features which are not available on the host FPGA and to prototype novel FPGA architectures. In these usecases, the achievable clock frequencies of V-FPGA user applications are a major concern. The abstraction layer inherently induces overhead, but this aspect is reinforced by nonuniformity effects: When V-FPGA cells perform worse locally, basic architecture modeling generalizes these worst-case path delays to the whole device, limiting applications to a lower frequency than theoretically achievable. We propose three approaches to attenuate these effects: First we introduce uniformity metrics and manual V-FPGA placement strategies for more uniform placement, improving achievable frequency by 16 %. Second, we propose a framework for automated timing extraction, enabling individual characterization of each V-FPGA design. Third, after evaluating Vivado synthesis strategies, we extend the timing model for non-uniform timings, achieving improvements of up to 28 %.

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A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization

Cited by 4 publications

References 8 publications

Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA

Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA

Design Concepts for a Virtualizable Embedded MPSoC Architecture

V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling

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