A portable and fault-tolerant microprocessor based on the SPARC v8 architecture

Gaisler, J.

doi:10.1109/dsn.2002.1028926

Cited by 152 publications

(130 citation statements)

References 9 publications

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“…The DLX core is a 32-bit 5-stage in-order single-issue pipeline running the MIPS-Lite ISA. Finally, the LEON3 is a system-onchip including a 32-bit 7-stage pipelined processor running the SPARC V8 architecture, an on-chip interconnect, basic peripherals and a memory controller [10]. The LEON3 SoC is capable of booting an unmodified version of Linux 2.6.…”

Section: A Experimental Methodologymentioning

confidence: 99%

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CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework

Pellegrini

Constantinides

Zhang

et al. 2008

2008 IEEE International Conference on Computer Design

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Abstract-Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures, gate-oxide wearout, and transient faults are becoming increasingly common. In order to overcome these issues and develop robust design techniques for large-market silicon ICs, it is necessary to rely on accurate failure analysis frameworks which enable design houses to faithfully evaluate both the impact of a wide range of potential failures and the ability of candidate reliable mechanisms to overcome them. Unfortunately, while failure rates are already growing beyond economically viable limits, no fault analysis framework is yet available that is both accurate and can operate on a complex integrated system.To address this void, we present CrashTest, a fast, highfidelity and flexible resiliency analysis system. Given a hardware description model of the design under analysis, CrashTest is capable of orchestrating and performing a comprehensive design resiliency analysis by examining how the design reacts to faults while running software applications. Upon completion, CrashTest provides a high-fidelity analysis report obtained by performing a fault injection campaign at the gate-level netlist of the design. The fault injection and analysis process is significantly accelerated by the use of an FPGA hardware emulation platform. We conducted experimental evaluations on a range of systems, including a complex LEON-based systemon-chip, and evaluated the impact of gate-level injected faults at the system level. We found that CrashTest is 16-90x faster than an equivalent software-based framework, when analyzing designs through direct primary I/Os. As shown by our LEONbased SoC experiments, CrashTest exhibits emulation speeds that are six orders of magnitude faster than simulation.

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Section: A Experimental Methodologymentioning

confidence: 99%

“…Recently, a number of commercial microprocessors that employ fault-tolerant design techniques have appeared in the marketplace [10,15]. Furthermore, the research area of faulttolerant design is a well studied area and several solutions have been proposed in the literature [2,6,19].…”

Section: Introductionmentioning

confidence: 99%

CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework

Pellegrini

Constantinides

Zhang

et al. 2008

2008 IEEE International Conference on Computer Design

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“…The logic resource consumption is configurable in the range of 2000-3000 logic cells (LC). That size is 1/3 of the soft-core RISC processor LEON, see Gaisler (2002), that is used by ESA for space missions.…”

Section: The Java Processor Jopmentioning

confidence: 99%

Application Experiences with a Real-Time Java Processor

Schoeberl

2008

IFAC Proceedings Volumes

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In this paper we present three different industrial real-time applications that are based on an embedded Java processor. Although from different application domains all three projects have one topic in common: communication. Today's embedded systems are networked systems. Either a proprietary protocol is used due to legacy applications or for real-time aspects or standard Internet protocols are used. We present the challenges and solutions for this variety of protocols in small, memory constraint embedded devices.

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“…But logic elements and small arrays, which are the main contributors to the majority of the soft error FIT budget [49], are largely unprotected due to the huge cost of using hardened latches or codes. Hardened latches and parity/error correction codes have 20-30% overhead in terms of extra logic dedicated for error detection and recovery [15,44]. Hence, meeting the desired FIT budget for current and future multicore systems is a major challenge.…”

Section: Introductionmentioning

confidence: 99%