A power and temperature aware DRAM architecture

Liu, Song; Memik, Seda Öǧrenci; Memik, Gokhan

doi:10.1145/1391469.1391691

Cited by 13 publications

(8 citation statements)

References 8 publications

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“…The idea behind the TA-MWB is similar to the idea behind the Page Hit Aware Write Buffer (PHA-WB) in our previous work [16][17]. The PHA-WB focuses on the improvement of DRAM power efficiency for all DRAM chips; while our proposed TA-MWB is tailored towards optimizing the power efficiency of DRAM chips under thermal stress.…”

Section: Temperature Aware Memory Write Buffermentioning

confidence: 99%

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Hardware/software techniques for DRAM thermal management

Liu¹,

Leung²,

Neckar

et al. 2011

2011 IEEE 17th International Symposium on High Performance Computer Architecture

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Section: Temperature Aware Memory Write Buffermentioning

confidence: 99%

“…However, such techniques are known to introduce system performance penalties, because their end effect is a direct reduction of DRAM accesses available per unit time. Our previous work [16][17] inserts a buffer to improve page hit rate. This in turn reduces power consumption and thermal dissipation.…”

Section: Related Workmentioning

confidence: 99%

Hardware/software techniques for DRAM thermal management

Liu¹,

Leung²,

Neckar

et al. 2011

2011 IEEE 17th International Symposium on High Performance Computer Architecture

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“…Since delaying write operations won't give much penalty to the overall performance, Ref. [34] proposes to add a write buffer between the processor and DRAM to improve row buffer hit rate and thus to reduce DRAM power consumption. Ref.…”

Section: B Hardware Approaches To Reduce Memory Power Consumptionmentioning

confidence: 99%

Energy and thermal aware buffer cache replacement algorithm

Yue

Zhu

Cai

et al. 2010

2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST)

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Power consumption is an increasingly impressing concern for data servers as it directly affects running costs and system reliability. Prior studies have shown most memory space on data servers are used for buffer caching and thus cache replacement becomes critical. Temporally concentrating memory accesses to a smaller set of memory chips increases the chances of free riding through DMA overlapping and also enlarges the opportunities for other ranks to power down. This paper proposes a power and thermal-aware buffer cache replacement algorithm. It conjectures that the memory rank that holds the most amount of cold blocks are very likely to be accessed in the near future. Choosing the victim block from this rank can help reduce the number of memory ranks that are active simultaneously. We use three real-world I/O server traces, including TPC-C, LM-TBF and MSN-BEFS to evaluate our algorithm. Experimental results show that our algorithm can save up to 27% energy than LRU and reduce the temperature of memory up to 5.45 o C with little or no performance degradation.

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“…[8] considers the power cost of opening and closing pages, and [12] proposes a Page Hit Aware Write Buffer (PHA-WB), a 64-entry structure residing between the memory controller and DRAM, which holds onto writes until their target page is opened by a read. The PHA-WB, however, was evaluated for a write-through cache, for which memory-level access locality will be much more apparent than in a writeback structure.…”

Section: Related Workmentioning

confidence: 99%

The virtual write queue

Stuecheli¹,

Kaseridis

Daly³

et al. 2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

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In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU's data needs, and are mostly oblivious to the main memory. In this paper, we demonstrate that the era of many-core architectures has created new main memory bottlenecks, and mandates a new approach: coordination of cache policy with main memory characteristics. Using the cache for memory optimization purposes, we propose a Virtual Write Queue which dramatically expands the memory controller's visibility of processor behavior, at low implementation overhead. Through memory-centric modification of existing policies, such as scheduled writebacks, this paper demonstrates that performancelimiting effects of highly-threaded architectures can be overcome. We show that through awareness of the physical main memory layout and by focusing on writes, both read and write average latency can be shortened, memory power reduced, and overall system performance improved. Through full-system cycle-accurate simulations of SPEC cpu2006, we demonstrate that the proposed Virtual Write Queue achieves an average 10.9% system-level throughput improvement on memory-intensive workloads, along with an overall reduction of 8.7% in memory power across the whole suite.

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A power and temperature aware DRAM architecture

Cited by 13 publications

References 8 publications

Hardware/software techniques for DRAM thermal management

Hardware/software techniques for DRAM thermal management

Energy and thermal aware buffer cache replacement algorithm

The virtual write queue

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