Hardware/software techniques for DRAM thermal management

Liu, Song; Leung, Brian; Neckar, Alexander; Memik, Seda Öǧrenci; Hardavellas, Nikos

doi:10.1109/hpca.2011.5749756

Cited by 45 publications

(31 citation statements)

References 23 publications

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“…We show 2 Figure 22 in [12] and Figure 3 in [43] show that the maximum temperature of DRAM chips at the highest CPU utilization is 60-65 • C. While some prior works claim a maximum DRAM temperature over 80 • C [76], each DIMM in their system dissipates 15W of power. This is very aggressive nowadays -modern DIMMs typically dissipate around 2-6W (see Figure 8 of [17], 2-rank configuration same as the DIMM configuration of [76] this in Figure 5, which plots the temperature for a 24-hour period (left) and also zooms in on a 2-hour period (right).…”

Section: Temperature Dependence: Hot Cells Are Leakiermentioning

confidence: 79%

“…• C [11,12,43]. 2 We measured the DRAM ambient temperature in a server cluster running a memory-intensive benchmark, and found that the temperature never exceeds 34…”

Section: Temperature Dependence: Hot Cells Are Leakiermentioning

confidence: 99%

“…• C: according to previous studies [11,12,43] and our own measurements (Section 4.2), the ambient temperature around a DRAM chip is typically less than 55…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

194

328

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In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85• C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55• C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case.Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55• C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adaptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface.We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.

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Section: Temperature Dependence: Hot Cells Are Leakiermentioning

confidence: 79%

“…• C [11,12,43]. 2 We measured the DRAM ambient temperature in a server cluster running a memory-intensive benchmark, and found that the temperature never exceeds 34…”

Section: Temperature Dependence: Hot Cells Are Leakiermentioning

confidence: 99%

See 1 more Smart Citation

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

194

328

View full text Add to dashboard Cite

show abstract

“…Several previous studies try to reduce temperature of 2D DRAM (DIMMs: Dual In-line Memory Modules) [10,11]. In [10], DRAM memory system is controlled by dynamic thermal management (core gating and dynamic voltage and frequency scaling).…”

Section: Related Workmentioning

confidence: 99%

“…In [10], DRAM memory system is controlled by dynamic thermal management (core gating and dynamic voltage and frequency scaling). In [11], DRAM thermal management is carried out by DRAM-aware techniques (e.g., a new cache line replacement policy, new write buffer design, and page allocation techniques, etc.). However, the above mentioned techniques are geared toward the conventional 2D DRAM systems with DIMMs.…”

Section: Related Workmentioning

confidence: 99%

3D die-stacked DRAM thermal management via task allocation and core pipeline control

Yoon

Shim

Moon

et al. 2018

IEICE Electron. Express

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A major hurdle to adopt 3D stacked DRAM is a thermal problem particularly when the DRAM dies are stacked above the processor dies. Exacerbated thermal problems in DRAM cause another problem which increases refresh rates to ensure data integrity of DRAM cells. In this paper, we propose two efficient techniques to address the thermal problem in 3D die-stacked DRAM by suppressing adverse thermal impacts from the processor die. Our thermal-aware task mapping technique allocates tasks to cores by considering computation-intensiveness of the workloads to minimize thermal interactions. The workload-aware core pipeline control technique adjusts pipeline widths (fetch and issue widths) of processor cores considering the workload characteristics. By adopting our proposed techniques, system-wide energy consumption is reduced by 7.6% while improving performance by 0.4% on average, thanks to the reduced pipeline widths and refresh rates. In terms of temperature, our techniques reduce the number of DRAM banks which exceed 85 degree Celsius by 92.8%, on average.

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Co‐scheduling of data intensive jobs and processor redistribution under temperature constraints

Ramesh

Suresh²

2018

Concurrency and Computation

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SummaryWith the congregation of more and more data intensive computational task in cloud environment, the distributive paradigm of data processing acquire the state of being more cost‐sensitive in commercial cloud computing environment. Also, the rise in power density from physical machines and memory systems has caused the development of mechanisms to cater efficient thermal management system. Owing to the reactive nature, these methods usually suffer from poor predictability; hence, there lies a dearth of availability of such mechanism to efficiently co‐schedule data intensive jobs and thermal management of physical computational cores in order to establish a workflow which guarantee in managing scheduling operations under time critical situations and thermal constraints. In this study, we present a reinforcement learning inspired heuristic reduction to co‐schedule such operations in near real‐time scenario. While this problem is, in general sense, corresponding to NP‐Hard problem, but the pluggable co‐scheduler so presented in this study can provide significant savings in affordable computational time under temperature constraints.

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Hardware/software techniques for DRAM thermal management

Abstract: The performance of the main memory is an important factor on overall system performance.

Cited by 45 publications

References 23 publications

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

3D die-stacked DRAM thermal management via task allocation and core pipeline control

Co‐scheduling of data intensive jobs and processor redistribution under temperature constraints

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