A power-optimal repeater insertion methodology for global interconnects in nanometer designs

Banerjee, Kaustav; Mehrotra, Amit

doi:10.1109/ted.2002.804706

Cited by 285 publications

(181 citation statements)

References 17 publications

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“…The related structure is named as "Unequal buffer partitioning network" against "Equal buffer partitioning network" that was mentioned above. The optimum delay is a function of various parameters such as the buffers sizes, the interconnect segments lengths, the load and so on [9], [11], [12], [15]- [17], [19]- [22]. It is shown that for the optimization of a buffer inserted interconnect behavior, the energy-delay product minimization is better than the delay minimization.…”

Section: Repeater Insertion As a Technique For The Delay Reductionmentioning

confidence: 99%

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Fathi¹,

Forouzandeh²

2010

Carbon Nanotubes

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This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented. Interconnect Challenges in VLSI CircuitsAs interconnect feature sizes shrink, copper resistivity increases due to surface and grain boundary scatterings and also surface roughness [1]. Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid increases in current densities [2]. The resistance of copper interconnects, with crosssectional dimensions of the order of the mean free path of electrons (~40 nm in Cu at room temperature) in current and imminent technologies [2], is increasing rapidly under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of the highly resistive diffusion barrier layer [3]. The steep rise in parasitic resistance of copper interconnects poses serious challenges for interconnect delay [2]

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Section: Repeater Insertion As a Technique For The Delay Reductionmentioning

confidence: 99%

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Fathi¹,

Forouzandeh²

2010

Carbon Nanotubes

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“…By tuning wire's characteristics, it is possible to design wires with varying latency, bandwidth, and energy properties [3]. Using links that are comprised of wires with different physical properties, a heterogeneous on-chip interconnection network is obtained [7].…”

Section: Introductionmentioning

confidence: 99%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

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Continuous improvements in integration scale have made possible the inclusion of several processor cores on the same chip. Such designs have been named chip-multiprocessors (or CMPs) and constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and increasing number of transistors available on a single chip have revealed energy consumption as a critical design issue in current and future microarchitectures. In these architectures, the design of the on-chip interconnection network has proven to have significant impact on overall system performance and energy consumption, and that the wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics.In this work, we present a detailed characterization of the energy-efficiency of a CMP for parallel scientific applications using Sim-PowerCMP, a detailed architectural-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, Hot Leakage and Orion) into a single framework that allows precise analysis and optimization of power dissipation (both dynamic and static) taking into account performance. In this characterization, we pay special attention to the energy consumed on the interconnection network. Results for an 8-and 16-core CMP show that the most power consuming messages are the replies that carry data (almost 70% on average of the total energy consumed in the interconnect) although they represent 30% of the total number of messages. Furthermore, we show that using on-chip wires with varying latency, bandwidth, and energy characteristics can reduce the energy dissipated by the links of the interconnection network about 65% with an average impact of 10% in the execution time.

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“…Several circuit models have been proposed to compute the delay or power dissipation of repeaters such as the switch-level RC model [9], the generalized model considering slew rate [14], and the moment matching model [3]. Various design objectives are used such as delay minimization [4,12,19], power minimization [6,10,13,16,18], and cross-coupling noise reduction [1,7].…”

Section: Previous Researchmentioning

confidence: 99%

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Peng¹,

Liu²

2005

Proceedings. 42nd Design Automation Conference, 2005.

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This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines a local optimizer based on the dynamic programming technique and a global search engine using the ellipsoid method. As a result, our approach is capable of producing high-quality solutions at a very fast speed. Furthermore, our scheme is robust and does not need any manual tuning of the iteration-control parameters.We have developed a repeater insertion tool, called FREEZE, using the proposed algorithm and applied it to various interconnect trees with different timing targets. Experimental results demonstrate the high effectiveness of our approach. In comparison with the state-of-the-art low-power repeater insertion schemes, FREEZE requires 5.8 times fewer iterations on the average, achieving up to 27 times speedup with even better power savings. When compared with a dynamic programming based scheme, which guarantees the optimal solution, our tool delivers up to 50 times speedup with 0.9% power increase on the average.

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A power-optimal repeater insertion methodology for global interconnects in nanometer designs

Cited by 285 publications

References 17 publications

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

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