A Practical Approach to Single Event Transients Analysis for Highly Complex Designs

Abstract

ISBN 978-1-4577-1713-0International audienceSingle Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

“…The MegaFIT (10 6 FIT) rate of the FreePDK45 cell library was calculated by Alexandrescu et al Alexandrescu et al (2011). Combining the data from that study with the cell frequency data introduced in the previous section shows that the area-constrained implementations have a higher FIT rate than the timing-constrained implementations (Figures 6.3 and 6.4).…”

“…However, the soft error rate of the cell library used in this study, FreePDK45, has been previously estimated (Alexandrescu et al, 2011). In the study by Alexandrescu …”

“…For example, the results from Alexandrescu et al (Alexandrescu et al, 2011) showed that for the FreePDK45 cell library, the XOR cell has a highest SER of any logic cell used in their study. Since the area-constrained implementations have a greater percentage (and total number) of XOR cells, the areaconstrained implementations can be predicted to have a higher SER.…”

“…Although the data from Alexandrescu et al (Alexandrescu et al, 2011) provide a soft error rate to compare cells, the latch-window masking contribution cannot be determined because the pulse width information is not available. The worst-case pulse width is determined to estimate this contribution.…”

“…It has been used to characterize the vulnerability of logic cells to soft errors (Alexandrescu et al, 2011). The study in this dissertation used a subset composed of five two-input logic functions.…”