A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation

Griffin, M.; Zerbe, J.; Chan, Alan; Jun, Yang; Tanaka, Y.; Richardson, W. S.; Tsang, G.; Ching, Michael; Portmann, C.; Li, Y.-X.; Stonecypher, Byron; Lai, Luhua; Lee, K.H.; Lee, V.; Stark, D.; Modarres, H.; Batra, Priya; Louis-Chandran, J.; Privitera, J. P.; Thrush, T.; Nickell, B.; Yang, Jun; Hennon, V.; Sauve, R.

doi:10.1109/4.726569

Cited by 15 publications

(6 citation statements)

References 9 publications

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“…higher sensitivity can be gained compared to previous V t measurement circuits [7]. Moreover, by using a saturation mode PMOS load to mirror the bias current, 2x higher gain is achieved compared to the previous linear mode PMOS load implementation [8].…”

Section: Introductionmentioning

confidence: 87%

“…The large swing in the output voltage with respect to process variation also attributes to the PMOS load in saturation mode. The key accomplishments that we have made in the new leakage sensor design are; (i) 10.2X higher sensing gain compared to previous V t measurement circuit in [7] (DIBL=98mV/V @ 0.13µm), (ii) 1.9X higher sensing gain compared to previous designs with grounded PMOS loads in [8] since the saturation mode PMOS in the current mirror offers higher gain, and (iii) low sensitivity to supply and P/N skew variations by using a comparator and PV insensitive bias generators. ).…”

Section: Leakage Sensor Design For Process Variation Detectionmentioning

confidence: 98%

“…This also guarantees that the monotonically increasing V SEN across the 6 channels do not swap levels under worst-case WID parameter variations. Since the proposed current mirror based design shares the bias circuits (I REF , V BIAS ) across each sensing channel, the leakage sensor circuit becomes simple and dense compared to [7] where separate V BIAS generators are required for each channel. Outputs of the comparators should be a thermometer code with a single transition.…”

Section: Leakage Sensor Design For Process Variation Detectionmentioning

confidence: 99%

“…It also requires multiple V BIAS generators when expanded to multi-bit resolutions, increasing both the area and design complexity. The vulnerability to supply voltage and P/N skew variations, and the multiple bias generator requirements are solved in [7] by replacing the PMOS load with a PV insensitive I REF and using a comparator instead of a static inverter (Fig. 7 (b)).…”

Section: Leakage Sensor Design For Process Variation Detectionmentioning

confidence: 99%

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Self calibrating circuit design for variation tolerant VLSI systems

Kim

Hsu

Krishnamurthy

et al. 2005

11th IEEE International on-Line Testing Symposium

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Increasing leakage current and aggravating process variations are showing impact on dynamic circuit performance and robustness as technology scales into the nanometer regime. This paper describes a self-calibrating process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage enables 10% faster performance, 35% reduction in delay variation, and 5X reduction in the number of robustness failing dies compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. The proposed 6-channel leakage current sensor enables high-resolution on-chip leakage measurements from multiple locations of a die, saving testing cost and realizing both die-to-die and within-die process compensation. Results based on measured leakage data show 1.9-10.2X higher signal-to-noise ratio and reduced sensitivity to supply and P/N skew variations compared to prior leakage sensor designs. The PCD technique with the on-die leakage current sensor is applied to a 2-read, 2-write ported 128x32b register file and a test chip is fabricated in 1.2V, 90nm dual-V t CMOS process.

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Section: Introductionmentioning

confidence: 87%

Section: Leakage Sensor Design For Process Variation Detectionmentioning

confidence: 98%

Section: Leakage Sensor Design For Process Variation Detectionmentioning

confidence: 99%

Section: Leakage Sensor Design For Process Variation Detectionmentioning

confidence: 99%

See 2 more Smart Citations

Self calibrating circuit design for variation tolerant VLSI systems

Kim

Hsu

Krishnamurthy

et al. 2005

11th IEEE International on-Line Testing Symposium

View full text Add to dashboard Cite

show abstract

“…Several metrics have been proposed in the literature to compare the noise immunity of the dynamic gates [46]. The wellknown noise-margin metric is the Unity Noise Gain (UNG) as used in [19,33].…”

Section: Noise Immunity Metricmentioning

confidence: 99%

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Asyaei

2015

Integration, the VLSI Journal

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Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Peiravi

Asyaei

2012

IEEJ Transactions Elec Engng

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Dual-rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual-rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan-in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual-rail circuits such as differential domino logic and differential cross-coupled domino logic. Simulation results for 32-bit-wide OR gates designed using high-performance 16-nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise-immunity improvement at the same delay compared to the differential domino circuits.

show abstract

A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation

Cited by 15 publications

References 9 publications

Self calibrating circuit design for variation tolerant VLSI systems

Self calibrating circuit design for variation tolerant VLSI systems

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

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