A process-variation-tolerant dual-power-supply SRAM with 0.179&amp;#x00B5;m&lt;sup&gt;2&lt;/sup&gt; Cell in 40nm CMOS using level-programmable wordline driver

Hirabayashi, O.; Kawasumi, A.; Suzuki, Ai; Takeyama, Y.; Kushida, K.; Sasaki, Tadahiro; Katayama, A.; Gou, Fujun; Fujimura, Y.; Nakazato, Tomoharu; Shizuki, Y.; Kushiyama, N.; Yabe, T.

doi:10.1109/isscc.2009.4977506

Cited by 59 publications

(26 citation statements)

References 8 publications

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“…The first is to increase the pass-gate to pullup ratio, however because we are operating in sub-threshold sizing is not an efficient knob. The second method is to collapse V DD , which weakens the pull-up transistors [4,9,10]. The third and fourth methods involve strengthening the pass-gate transistors by either boosting the WL V DD or reducing the BL V SS [4][5][6][7][8]11,13].…”

Section: Write Assist Methodsmentioning

confidence: 99%

“…The first is to improve the stability of the cross-coupled inverters during the read by either raising the bitcell V DD or reducing its V SS [4,5,[7][8][9][10]. While raising bitcell V DD has been shown by [2] to result in larger gains in RSNM, the advantage of reducing the bitcell V SS is that it significantly reduces read delay due to the body effect strengthening both the pull-down and pass-gate transistors [2].…”

Section: Read Assist Methodsmentioning

confidence: 99%

“…This paper provides a comparison of four different bitcell topologies using read and write V MIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4][5][6][7][8][9][10][11][12][13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV.…”

Section: Introductionmentioning

confidence: 99%

“…The downside to this strategy is that adding more transistors to the bitcell increases the total area of the array. The second strategy is to use various assist methods [4][5][6][7][8][9][10][11][12][13] to make the cell easier to read and write. This method also results in a smaller area overhead and may require multiple voltage sources.…”

Section: Introductionmentioning

confidence: 99%

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Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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Abstract:The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write V MIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4][5][6][7][8][9][10][11][12][13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write V MIN by 100 mV over the unassisted test case.

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Section: Write Assist Methodsmentioning

confidence: 99%

Section: Read Assist Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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“…Functionality and high yield at low supply voltages such as 0.7V has become more difficult to achieve with the degradation of write margin and the optimization between read disturb and write margin. Among recently reported techniques, the scheme that implements BL negative biasing and WL level control [4] is an effective approach [1]. However, the conventional schemes are not suitable for configurable SRAM for two reasons.…”

mentioning

confidence: 99%

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Fujimura

Hirabayashi

Sasaki

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-κ metal-gate CMOS technology with a 0.149µm 2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.For a low power SoC, a configurable SRAM operating at low voltage is a key component. The characteristic variation of a scaled device has been increasing, thus compromising the low-voltage functionality of high-density SRAMs [2,3]. Functionality and high yield at low supply voltages such as 0.7V has become more difficult to achieve with the degradation of write margin and the optimization between read disturb and write margin. Among recently reported techniques, the scheme that implements BL negative biasing and WL level control [4] is an effective approach [1]. However, the conventional schemes are not suitable for configurable SRAM for two reasons. First, the circuit must be optimized for each different array configuration to create a suitable BL level. Second, the conventional scheme of WL-level control causes rise-time degradation of the WL at low voltage. This paper describes two circuit techniques for coping with the problems, CNL-WB to automatically adjust the BL bias to a suitable level in a wide range of array configurations and LPWD-SS for fast WL activation at low voltage. Figure 19.4.1 shows the circuit schematic of the configurable SRAM. Each I/O block has the BL negative bootstrap circuit named CNL-WB. The BL capacitance monitor working as a replica of a BL generates a signal activating the bootstrap (boost_en). Every WL driver has a pull-down unit (PDU) to lower the WL voltage for optimizing the tradeoff between disturb and write margin. Figure 19.4.2 shows the circuit schematic and simulated waveforms of CNL-WB. One issue of the conventional technique [1] is as follows: when using a negative-bootstrap circuit in a configurable SRAM, the bootstrap capacitance and the timing of activating the signal boost_en must be optimized depending on the memory cell count on a BL. The custom optimization makes this technique unsuitable for compilable SRAMs. Without such optimization, the negative BL level can become too high and results in insufficient write margin. On the other hand, if the level is too low it causes a reliability problem through data corruption on memory cells with unselected WLs on the accessed column. CNL-WB solves this problem with a bootstrap circuit by automatically adjusting the BL ...

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Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

Zeinali

Madsen

Raghavan

et al. 2016

Circuit Theory & Apps

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Summary A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.

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A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Cited by 59 publications

References 8 publications

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

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A process-variation-tolerant dual-power-supply SRAM with 0.179&#x00B5;m<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Cited by 59 publications

References 8 publications

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149&#x00B5;m<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

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Product

Resources

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A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS