A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme

Chang, Meng‐Fan; Shen, Shin-Jang

doi:10.1109/jssc.2009.2013763

Cited by 37 publications

(8 citation statements)

References 21 publications

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“…However, they did not take, i.e., the specific strength of each individual block into consideration. PV has become significant among flash blocks, which introduces the variation in strength [5], [6], [13], [21]. The P/E cycling-induced wearing to a stronger block is smaller than it does to a weaker block, and the electronic leakages during retention time from a stronger block are much smaller than a weaker block.…”

Section: A Write Speed Detectionmentioning

confidence: 99%

“…Motivated by these works, this brief proposes to improve write performance by exploiting the process variation (PV) among blocks. The PV is a naturally occurring variation in the attributes of transistors [5], [6], [13]. With technology scaling and bit density improvement, the PV of flash memory has been magnified, especially for the number of available P/E cycles supported by different blocks [7], [17], [21].…”

Section: Introductionmentioning

confidence: 99%

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Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

Shi

Zhao

et al. 2016

IEEE Trans. VLSI Syst.

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The write performance of flash memory has been degraded significantly due to the recent density-oriented advancements of flash technology. Techniques have been proposed to improve the write performance by exploiting the varying strength of a flash block in its different worn-out stages. A block is written with a faster speed when it is new and strong, and gradually will be written with slower speeds as it is aging and becomes weak. Motivated by these works, this brief proposes a new technique by exploiting the significant process variation among flash blocks introduced by the advanced technology scaling. First, a write speed detection approach is proposed to identify the strength of each block. Then, a heuristic approach is proposed to exploit the speed variation among blocks for write performance improvement. A series of trace-driven simulations shows that the proposed approach generates substantial write performance improvement over state-of-the-art approaches by 30% on average.

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Section: A Write Speed Detectionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

Shi

Zhao

et al. 2016

IEEE Trans. VLSI Syst.

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“…The use of single-ended sensing in which the reference current generation circuit (replica bitline or dummy bitline/DBL) is shared by all CSAs [23], [24] can reduce the current consumption below that of conventional differential-input CSAs. This is achieved by eliminating the precharge operation for multiple DBLs, particular in high throughput applications.…”

Section: A Comparisonmentioning

confidence: 99%

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Chang

Lin

Liu

et al. 2015

IEEE J. Solid-State Circuits

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Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time , due to significant summed input offsets at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a improvement in using AVB-CSA with a BL-length of 2048-rows operating at V. Index Terms-Current-mode sense amplifier (CSA), Flash.

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“…Mobile system using nonvolatile memory (NVM) provides store programs and data in the power mode. The most commonly used NVM embedded logic-ROMs flash [1] and [2]- [6]. Clever use way can reduce the damage of the current system standby.…”

Section: Introductionmentioning

confidence: 99%

The Study on Embedded Memory Circuit Design in Low-power SoC Chips for Mobile Systems

Ren¹,

Song-liang²,

Shao³

2012

IJACT

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The most important characteristic is a battery of mobile communication system with high performance, low power consumption and small size. Small form factor, and realize the system chips (SoC) and 3 D die-stacking (3 D-IC) method is to use multiple-chip instead of traditional solutions. Discusses the low voltage memory challenge created the circuit design and new memory solution and 3 D-IC mobile system chip (SoC) application. We explore new processor-memory architecture interface and the memory of the mobile and 3 D-IC SoC design.

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A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme

Cited by 37 publications

References 21 publications

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

The Study on Embedded Memory Circuit Design in Low-power SoC Chips for Mobile Systems

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