A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells

Torsi, Alessandro; Zhao, Yijie; Liu, Haitao; Tanzawa, Toru; Goda, Akira; Kalavade, P.; Parat, Krishna

doi:10.1109/ted.2010.2087338

Cited by 45 publications

(18 citation statements)

References 6 publications

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“…A related effect has been noted in [278], where a negative V T shift contribution was found and explained in terms of hot-hole injection from the STI edge to the control-gate [279,280]. All this suggests that the detailed leakage mechanisms affecting the boosted channel potential must be studied with extreme care [281].…”

Section: Program and Pass Disturbsmentioning

confidence: 85%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Program and Pass Disturbsmentioning

confidence: 85%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…Since the 2nd page is set by two references, BER 2nd_page is calculated by summing the shifted cells in both N cellA and N cellB . Immediately after program, program-disturb's tendency to increase V TH is dominant [17], and the retention effect is negligible. For example, ''P2'' to ''P3'' and ''P6'' to ''P7'' errors are much higher than ''P3'' to ''P2'' and ''P7'' to ''P6'' errors, respectively when data-retention time is 1.45 s (Fig.…”

Section: Retention Time Estimation Unit (Unit 1)mentioning

confidence: 99%

“…1c, to correct errors caused by program-disturb, data-retention, as well as floating-gate capacitive coupling [3]. V TH is increased and shifted upwards due to program-disturb [17]. On the other hand, V TH is decreased and shifted downwards due to data-retention [18].…”

Section: Introductionmentioning

confidence: 99%

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Tokutomi

Tanakamaru

Iwasaki

et al. 2015

Solid-State Electronics

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a b s t r a c tTo improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012(Tanakamaru et al., , 2013, which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error. Therefore, advanced error-prediction LDPC (AEP-LDPC) has been proposed for TLC NAND Flash memory (Tokutomi et al., 2014). AEP-LDPC can correct errors more accurately by precisely describing the error phenomena. In this paper, the effects of AEP-LDPC are investigated in a 2Ânm TLC NAND Flash memory with temperature characterization. Compared with LDPC-with-BER-only, the SSD's data-retention time is increased by 3.4Â and 9.5Â at room-temperature (RT) and 85°C, respectively. Similarly, the acceptable BER is increased by 1.8Â and 2.3Â, respectively. Moreover, AEP-LDPC can correct errors with pre-determined tables made at higher temperatures to shorten the measurement time before shipping. Furthermore, it is found that one table can cover behavior over a range of temperatures in AEP-LDPC. As a result, the total table size can be reduced to 777 kBytes, which makes this approach more practical.

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“…A poor P/E window precludes MLC (Fig. 4) and a poor programming slope degrades the program disturb window [5] (Fig. 6).…”

Section: Program/erase Vt Window and Programming Slopementioning

confidence: 99%

Scaling directions for 2D and 3D NAND cells

Goda

Parat

2012

2012 International Electron Devices Meeting

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This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed. 2D NAND Cell ScalingStructure Fig. 1 shows cross sections of a wrap FG cell and a planar FG cell. The increase of aspect ratio (A.R.) is a key limiter for the wrap FG cell scaling (Fig. 2). A.R. becomes >10 for both the word-line and the bit-line directions in a sub-20nm wrap cell. The planar cell eliminates this limitation [1].

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A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells

Cited by 45 publications

References 6 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Scaling directions for 2D and 3D NAND cells

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