A proposed hardware reference model for spatial transformation and quantization in H.264

Amer, Ihab; Badawy, W.; Jullien, G.A.

doi:10.1016/j.jvcir.2005.05.011

Cited by 11 publications

(10 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…More concretely, they are programmed on field programmable gate arrays (FPGAs) (Bensaali and Amira, 2005;Isaacs et al, 2003). Some of the most recently used FPGA families are Xilinx Virtex-II (Amer et al, 2006;Moon and Sedaghat, 2006;Bojanis et al, 2006) and Virtex-E (Damaj, 2006;Perri et al, 2005).…”

Section: Real-time Hardware Implementation Of Motion-detection Liac Mmentioning

confidence: 99%

Real-time motion detection by lateral inhibition in accumulative computation

Delgado

López

Fernández-Caballero

2010

Engineering Applications of Artificial Intelligence

View full text Add to dashboard Cite

a b s t r a c tMany researchers have explored the relationship between recurrent neural networks and finite state machines. Finite state machines constitute the best characterized computational model, whereas artificial neural networks have become a very successful tool for modeling and problem solving. In the few last years, the neurally inspired lateral inhibition in accumulative computation (LIAC) method and its application to the motion detection task have been introduced. The article shows how to implement the tasks directly related to LIAC in motion detection by means of a formal model described as finite state machines. This paper introduces two steps towards that direction: (a) A simplification of the general LIAC method is performed by formally transforming it into a finite state machine. (b) A hardware implementation of such a designed LIAC module, as well as an 8 Â 8 LIAC module, has been tested on several video sequences, providing promising performance results.

show abstract

Section: Real-time Hardware Implementation Of Motion-detection Liac Mmentioning

confidence: 99%

Real-time motion detection by lateral inhibition in accumulative computation

Delgado

López

Fernández-Caballero

2010

Engineering Applications of Artificial Intelligence

View full text Add to dashboard Cite

show abstract

“…Nevertheless, hardware implementations are also desirable for consumer products since they provide consistent advantages in terms of compactness, low power, robustness, low costs, and, most importantly, real-time operation up to HDTV rates. In our previous work, [3][4][5][6][7][8] hardware implementations of different blocks in the initial H.264 transformation hierarchy model and entropy coding have been presented, while in Refs. 9 and 10, a design flow to accelerate the process of testing the quality of developed IP-blocks with the H.264 software reference model has been specified and described.…”

Section: Introductionmentioning

confidence: 99%

A Simplified 8 × 8 Transformation and Quantization Real-Time Ip-Block for Mpeg-4 H.264/AVC Applications: A New Design Flow Approach

Amer¹,

Badawy²,

Jullien³

et al. 2007

J CIRCUIT SYST COMP

Self Cite

View full text Add to dashboard Cite

Current multimedia design processes suffer from the excessively large time spent on testing new IP-blocks with references based on large video encoders specifications (usually several thousands lines of code). The appropriate testing of a single IP-block may require the conversion of the overall encoder from software to hardware, which is difficult to complete in the short time required by the competition-driven reduced time-to-market demanded for the adoption of a new video coding standard. This paper presents a new design flow to accelerate the conformance testing of an IP-block using the H.264/AVC software reference model. An example block of the simplified 8 × 8 transformation and quantization, which is adopted in FRExt, is provided as a case study demonstrating the effectiveness of the approach.

show abstract

“…The DC component is not considered to embed the watermark because it introduces the visual distortion that degrades the quality of a frame. Therefore 5 AC values AC (0,1) , AC (1,0) ,AC (0,2), AC (2,0) and AC (1,1) of low frequencies are chosen to embed the watermark.…”

mentioning

confidence: 99%

“…AC i are the original AC components defined as AC (0,1) , AC (1,0) , AC (0,2) , AC (2,0) and AC (1,1) . AC i ′ is the estimation of AC i where i=(0,1),(1,0),(0,2),(2,0) and (1,1).…”

mentioning

confidence: 99%

FPGA prototyping of video watermarking for ownership verification based on H.264/AVC

Joshi

Mishra

Patrikar

2015

Multimed Tools Appl

View full text Add to dashboard Cite

Digital video watermarking has drawn the attention towards authentication and proof of ownership. Uncompressed domain watermarking has flourished over the years and related algorithms have been implemented on the software platform. Software watermarking algorithms work offline where videos are captured through device and embedding algorithms run on a PC that is used to embed the watermark in the original video content. It doesn't suffice real time requirements because of the delay that takes place between capturing and embedding the watermark. This delay involvement is more prone to attacks. Thus, it is essential to develop the system where the watermark gets embedded at the same time when video is being captured. In this paper, an efficient watermark embedding process has been portrayed which is suited to H.264/AVC standard. The proposed algorithm introduces the concept of scene change detection based on Integer Discrete Cosine Transform (Integer-DCT) using scene change detection. The different frames of a scene are embedded with different bit planes of the same watermark in order to improve the performance against temporal attacks. The algorithm is validated on the MATLAB platform and is prototyped on FPGA to show its feasibility for real-time application.

show abstract

A proposed hardware reference model for spatial transformation and quantization in H.264

Cited by 11 publications

References 9 publications

Real-time motion detection by lateral inhibition in accumulative computation

Real-time motion detection by lateral inhibition in accumulative computation

A Simplified 8 × 8 Transformation and Quantization Real-Time Ip-Block for Mpeg-4 H.264/AVC Applications: A New Design Flow Approach

FPGA prototyping of video watermarking for ownership verification based on H.264/AVC

Contact Info

Product

Resources

About