A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM

Abstract

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with railto-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180 nm CMOS. Laboratory measurement shows a power consumption of 1.35 mW from a 1.2 V supply at 4.6 GHz. The proposed PTFB-VCO achieves a flicker corner of 700 Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of −195 dB within a wide offset frequency range of 1 kHz-10 MHz.

Switched-Biasing Techniques for CMOS Voltage-Controlled Oscillator

“…Low impedance at the common node may cause the deduction of the phase noise as more noise from the switching operation of the current source affects the VCO core [ 58 ]. The effect on impedance reduction at the common node by DC biasing near the threshold voltage may be minimized as proposed by the previous studies, which include the method of splitting the current source into several transistors, the method of using a source degeneration capacitor, and the method of implementing an additional filter for noise reduction [ 52 , 54 , 58 , 60 , 64 ].…”

“…It was shown that the self-biasing topology implementing adaptive DC biasing using a negative peak detector can compensate for PVT variation and the variation of the Q-factor of the varactor that occurs in tuning the oscillation frequency [ 63 ]. A self-biasing topology with a pulse generator with three different operating states has been proposed to achieve a low conduction angle in steady state and a fast start-up time [ 64 ]. As the main drawback, the auxiliary circuit to implement the adaptive DC biasing requires additional loading to reduce the Q-factor of the LC tank and tuning range and increases the power consumption.…”

“…The high FoM of −190 dBc is based on the phase noise reduction by the switched-biasing technique along with the reduction in the intrinsic noise and current consumption by using a PMOS current source operating in the triode mode [ 54 , 60 ]. The high FoM and FoM T of the VCO with the adaptive DC voltage, high modulation amplitude, and pulse waveform in the self-biasing topology show that the minimum conduction angle can be useful for improving the VCO performance [ 64 ]. Figure 17 shows that the performance of the VCO can be improved by reducing the noise injection when the modulation waveform is implemented as a pulse with a duty cycle of less than π in the switched-biasing technique [ 64 ].…”

“…Narayanan and Okada presented the VCO architecture using a synchronized pulse generator to inject pulse-shaped waveforms into each current source, as shown in Figure 14 [ 64 ]. Unlike the self-biasing with the fixed DC voltage in which a modulation signal is injected directly through a capacitor, a rail-to-rail waveform is implemented using a two-stage inverter to narrow the conduction angle.…”

“…However, the intrinsic delay of the pulse generator clarifies the limitations of this method, as shown in Figure 14 c. For proper current bias based on the ISF theory, a positive peak voltage must be delivered to the current source at the point where the ISF is zero crossing, but an indispensable mismatch occurs because of the corresponding delay. The result is shown in detail in Figure 14 d. By adjusting the delay of the pulse waveform modeled with Verilog-A, when the delay exceeds 8/π, the phase noise degradation occurs rapidly, and even when it reaches 4/π, it can be observed that oscillation does not occur [ 64 ].…”