A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty

Abstract

The push for 100Gb/s optical transport and beyond necessitates electronic components at higher speed and integration level in order to drive down cost, complexity and size of transceivers [1][2]. This requires parallel multi-channel optical transceivers each operating at 25Gb/s and beyond. Due to variations in the output power of transmitters and in some cases different optical paths the parallel receivers have to operate at different input optical power levels. This trend places increasing strain to the acceptable inter-channel crosstalk in integrated multichannel receivers [3]. Minimizing this cross-talk penalty when all channels are operational is becoming increasingly important in ultra-high throughput optical links.One of the fundamental sources of crosstalk in multi-channel optical receivers stems from the fact that the photodiode provides a single-ended current and the transimpedance stage is single-ended. The single-ended to differential conversion occurs at a later stage. While this practice has proven adequate for singlechannel TIAs, it poses significant cross-talk risks in a multi-channel environment, where multiple TIAs are integrated on the same die. The worst-case penalty occurs when one channel operates close to sensitivity and all others at the maximum acceptable input optical modulation amplitude (OMA). This paper describes a transimpedance architecture that outputs a differential signal directly at the input stage. We implement this topology in a four-channel 25Gb/s TIA dissipating 83mA from 3.3V with a 0.15dB inter-channel crosstalk penalty (as defined by IEEE 802.3ba [4]) and better than -12dBm OMA sensitivity for all channels.Figure 7.1.1 shows the receiver optical sub-assembly (ROSA) that houses the quad-TIA (QTIA). A four-wavelength optical signal is demultiplexed into its four distinct wavelengths. The four beams are then steered and focused using a prism and a collimator into the active areas of a 4-channel photodiode (PD) array. The PD capacitance is 65fF and its responsivity 0.75A/W. The PD channel pitch is 750μm. The PDs are then bonded to QTIA inside the ROSA. The block diagram of a single channel is also shown in Fig.7.1.1. The PD cathode bias is provided by a low drop-out regulator off a separate supply. The input stage transimpedance gain is 800Ω. The second stage is a Cherry-Hooper amplifier with a gain of 6, and the output is a 50Ω CML stage with a gain of 1.4. The combined transimpedance is 6.7kΩ. The bandwidth of the receiver is 23GHz, the low-frequency cut-off is 22kHz and the input-referred noise 2.4μA rms (sensitivity of -13.5dBm OMA) in simulation.The input stage circuit is shown in Fig. 7.1.2. Input device Q 1 is configured as a common-base (CB) amplifier. The voltages at the output of the first stage are v 1p = i IN R 1 and v 1n = -(g m2 /g m1 )i IN R 2 resulting in a transimpedance gain of R T = R 1 + (g m2 /g m1 )•R 2 . For R 1 = (g m2 /g m1 )•R 2 the signals v 1p and v 1n are fully differential. Capacitor C 1 bootstraps Q 2 to Q 1 such that any voltage variation at the...

Power‐efficient low‐noise 86 GHz broadband amplifier in 130 nm SiGe BiCMOS

“…Using (1), and assuming a photodetector (PD) responsivity of 1 A/W, and following [6] we can estimate that the average optical power sensitivity would be −14.6 dBm if the PD is closely integrated with the amplifier and the PD assumes similar capacitance (∼40 fF) as the pads that currently exist in the layout. This sensitivity is comparable to or better than the state‐of‐the‐art transimpedance amplifier and optical receiver results at much lower data rates [6–8].…”

A 25-Gb/s high-sensitivity transimpedance amplifier with bandwidth enhancement

“…For high-speed TIA, achieving maximum bit rates requires a flat response of the magnitude of the transimpedance within the frequency range of interest. The use of networks, such as T-coil peaking, shunt-series peaking, shunt-peaking, and π-type peaking, have been reported to increase the bandwidth and remove the passband ripple [15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]. However, the bondwire inductance and the parasitic capacitance of the PD vary from chip to chip in engineering applications; thus, the TIA should be designed to be robust to these variations.…”

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

“…In practice, a quad 25-Gb/s per channel is a possible solution for the purpose [2][3]. Yet, efforts have been conducted to increase the bandwidth further and also to decrease power consumption simultaneously.…”