A Quasi-Two-Dimensional Compact Drain–Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects

Lime, F.; Iñı́guez, Benjamı́n; Moldovan, Oana

doi:10.1109/ted.2008.921980

Cited by 58 publications

(36 citation statements)

References 15 publications

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“…CaugheyThomas mobility model was employed in this simulation since it has been frequently used to describe the transport in GAA device. [25][26][27] It also being utilized for its dependency on velocity saturation at high longitudinal field and on channel length modulation (CLM). Shockley-Read-Hall (SRH) Recombination with fixed carrier lifetimes models was evoked since its take into account the phonon transitions effect due to the presence of traps (or defects) within the forbidden gap of a semiconductor.…”

Section: Simulation Proceduresmentioning

confidence: 99%

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) with low-k SiO 2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler-Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO 2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO 2 has been obtained using SiO 2 / Al 2 O 3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6 V gate stress.

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Section: Simulation Proceduresmentioning

confidence: 99%

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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“…In [19], a description of Short-Channel Effects (SCE) in subthreshold region, including Drain Induced Barrier Lowering (DIBL), sub-threshold swing and mobility degradation [1], enters into the expressions of charge and current. SCE are also a subject of [20] while quantum effects (carrier quantization) are treated and included in the models presented in [21]- [24]. Given the structural similarities between DG MOSFET and FinFET, several models for the latter are directly derived from the models for the former (if the top gate is sufficiently high to neglect the edge effects).…”

Section: B Multi-gate Device Modelsmentioning

confidence: 99%

Computationally Efficient Multiple-Independent-Gate Device Model

Antidormi

Frache

Graziano

et al. 2016

IEEE Trans. Nanotechnology

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Abstract-Nanowire Field Effect Transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control and are regarded as promising candidates for next generation transistors. Being inherently more complex than conventional gate-all-around nanowire FETs, they require longer simulation times, especially with numerical simulations. We present a new model enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on Gate-All-Around MOSFETs, FinFETs and gate-less channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators.

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“…This corresponds to the boundary case of the symmetric DGMOS. Therefore, in order to avoid singularities in the model, we impose a minimum value to Q 0 , corresponding to the one obtained for the symmetrical case: 2bC si [15,16]. Therefore, Q 0 is approximated as:…”

Section: Long Channel Charge Modelmentioning

confidence: 99%

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

Lime

Ritzenthaler

Ricoma

et al. 2011

Solid-State Electronics

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A Quasi-Two-Dimensional Compact Drain–Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects

Cited by 58 publications

References 15 publications

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Computationally Efficient Multiple-Independent-Gate Device Model

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

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