A Radix-10 Combinational Multiplier

Abstract

Abstract-In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.

A New Family of High.Performance Parallel Decimal Multipliers

“…It uses BCD-8421 invalid combinations to simplify the sum digit logic. A combinational radix-10 CSA tree is implemented in [8] using these 4-bit decimal carry-propagate adders. To optimize the partial product reduction they also use an array of decimal digit counters.…”

“…So far, the only known fully parallel implementation of a decimal multiplier is [8]. The recoding and the generation of partial products is practically similar to our SD radix-5 recoding scheme except that [8] requires a 9's complement operation to obtain negative multiples −2X and −X.…”

“…The recoding and the generation of partial products is practically similar to our SD radix-5 recoding scheme except that [8] requires a 9's complement operation to obtain negative multiples −2X and −X. For 16 decimal digits, 32 partial products are generated.…”

“…However, due to the inherent in-efficiency of decimal arithmetic implementations in binary logic, practically all the proposed decimal multipliers are sequential units [2,4,7,9,11,16]. Recently, the first implementation of a parallel decimal multiplier was presented in [8]. Parallel multipliers are used extensively in most of the binary floating-point units [10,13] and are of interest for decimal applications to scale performance.…”

A parallel IEEE P754 decimal floating-point multiplier

“…A few parallel fixed-point multiplier designs have also been proposed [1,13]. The floating-point multiplier presented in this paper is based on the radix-10 fixed-point multiplier in [1] due to its highly efficient structure.…”