A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration

Scalable Parallel Distributed Coprocessor System for Graph Searching Problems with Massive Data

“…A considerable amount of research on parallel BFS implementations on GPUs focuses on level-synchronous or fixed-point methods [19,20]. The reconfigurable hardware approach in solving graph traversal problems on clusters of FPGAs is limited by graph size and synthesis times [4,8]. Betkaoui et al (2012) [4] and Attia et al (2014) [8] explored highly parallelized processing elements (PEs) and decoupled computation memory.…”

“…However, new parallel computing machines could provide a better platform for software methods. Heterogeneous processing, with reconfigurable logic and field-programmable gate array (FPGAs) as an energy efficient computing systems [7], performs competitively with the multicore CPUs and GPGPUs [4,8]. The performance of breadth-first search (BFS) on large graphs is bound by the access to high-latency external memory.…”

“…These applications represent the connections, relations, and interaction among entities, such as social networks [2], biological interactions [3], and ground transportation [1]. Poor data-driven computation, unstructured organization, irregular memory access, and low computations-to-memory ratio are the prime reasons for parallel large-graph processing inefficiency [4]. To traverse larger graphs caused by dataintensive applications, a variety of scientific programming methods has been proposed [5,6].…”

Parallel graph traversal for FPGA

“…Set the vertex number to 16 million with an average arity from 8 to 32, we compare the BFS performance on our platform to that of ASAP12-1F, as shown in Table. III. ASAP12-1F, the single FPGA-based implementation of [5], is a state-of-the-art highly optimized BFS implementation on FPGA for large scale graphs, which is capable of obtaining superior performance to that of multi-core CPU platforms. Using a single Virtex5 LX330 FPGA with 32 PEs, our design outperforms ASAP12-1F using the same type of FPGA with 128 PEs by a factor of 1.25x to 1.32x.…”

“…The early methods either build a circuit that resembles the graph or use low-latency on-chip memory resources to store the entire graph [1,2,3], but failed to adapt the real world graphs, which are too large to fit into on-chip random-access memory (RAM) of FPGAs. Several recent publications [4,5] described strategies of graph traversal on FPGAs using off-chip DRAM memories to adapt the traversal of large-scale graph instances, and Betkaoui's work [5] is the first FPGA-based BFS implementation that can compete with other high performance multi-core systems.…”