A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

“…Its functionality and structure is the same as the block denoted as R select in CNU. This unit can be treated as a de-compressor of the check-node edge information, which is stored in compact form in FS memory.It is possible to do the decoding using a different sequence of layers instead of processing the layers from 1 to j which is typically used to increase the parallelism such that it is possible to process two block rows simultaneously [4]. In this work, we use the concept of re-ordering of layers for increased parallelism as well as for low complexity memory implementation and also for inserting additional pipeline stages without incurring overhead.…”

“…This essentially doubles the throughput when compared to the TDMP architecture. Moreover, this architecture requires only one cyclic shifter instead of two cyclic shifters [2], [4]. Note that the architecture features a partial state memory when compared to other architectures.…”

Low Complexity LDPC Code Decoders for Next Generation Standards

“…WiFi IEEE 802.11n) where the latency budget for channel decoding is poor (6 µs or less). In layered decoding [11,17] the parity check matrix is considered as being made of a sequence of horizontal or vertical layers, hence the names of horizontal and vertical shuffle also used to indicate this technique. The layered decoding principle for horizontal layers is expressed by:…”

“…The key point of the layered schedule is the intermediate update, within an iteration, of the SO estimates and their propagation to the next layers, boosting the convergence speed and saving up to 50% of the iteration time [11].…”

Architecture and Finite Precision Optimization for Layered LDPC Decoders

“…The FEC supports eleven code rates for the DVB-S2 standard and is reduced to six code rates for the DVB-T2 standards. The LDPC codes defined by the DVB-S2,-T2,-C2 standards are structured codes or architecture-aware codes (AA-LDPC [3]) and can be efficiently implemented using the layered decoder architecture [4], [5] and [6]. The layered decoder benefits from three architecture improvements: parallelism of structured codes, turbo message passing, and Soft-Output (SO) based Node Processor (NP) [4], [5] and [6].…”