A Review of Spiking Neuromorphic Hardware Communication Systems

Young, Aaron; Dean, Mark E.; Plank, James S.; Rose, Garrett S.

doi:10.1109/access.2019.2941772

Cited by 91 publications

(52 citation statements)

References 39 publications

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“…They are also the best prototypes for implementing machine learning algorithms and offering remarkable real-time and parallel performances. [1][2][3][4] Some of the most significant spiking neuromorphic hardware systems currently used are Loihi, 5 TrueNorth, 6 and SpiNNaker. 7 Two significant reasons for employing SNNs in different engineering and computing applications are their biological inspiration and their power/ energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…13,14 Comprehension of spiking neurons and networks has stimulated important research on their implementation in both software and hardware, and numerous analog and digital implementations of these types of neurons and networks have been suggested. [1][2][3][4] Analog implementations have used resistors, transistors, and memristors as electronic elements, making this approach fast and power efficient but excessively inflexible. [15][16][17][18] On the other hand, field-programmable gate arrays (FPGAs) have emerged as reconfigurable general-purpose logic devices which can be reprogrammed by designers after fabrication for a wide range of applications.…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

Gholami

Farsa

Karimi

2021

Circuit Theory & Apps

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Hardware implementations of spiking neural networks, which are known as neuromorphic architectures, provide an explicit understanding of brain performance. As a result, biological features of the brain may well inspire the next generation of computers and electronic systems used in such areas as signal processing, image processing, function approximation, and pattern recognition. Approximating nonlinear functions has many uses in computer science and applied mathematics. The sigmoid is the most universal activation function in neural networks by which the relationship between biological and artificial neurons is defined. It is a suitable option for predicting the probability of anything from 0 to 1 as output. In this paper, a spiking neural network using Izhikevich neurons and a gradient descent learning algorithm are propounded to approximate the sigmoid and other nonlinear functions. The flexibility of the spiking network is demonstrated by showing the average relative errors in the approximation process. A time-and cost-efficient digital neuromorphic implementation on the base of on-chip learning method for approximating the sigmoid function is also discussed. The paper reports the results of the hardware synthesis and the spiking network's physical implementation on a field-programmable gate array. The maximum frequency and throughput of the implemented network were 83.209 MHz and 9.86 Mb/s, respectively. K E Y W O R D Sdigital hardware, field-programmable gate array (FPGA), hardware implementation, neuromorphic, on-chip learning, spiking neural networks (SNNs)

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

Gholami

Farsa

Karimi

2021

Circuit Theory & Apps

View full text Add to dashboard Cite

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“…Neuromorphic systems focus on the implementation of computational models based on Spiking Neural Networks (SNNs), a special type of neural network exhibiting asynchronous and sparse behavior. This event-driven approach, inspired by the human nervous system, ensures very low power consumption while allowing for efficient data exchange among several independent computational units [4].…”

Section: Introductionmentioning

confidence: 99%

PageRank Implemented with the MPI Paradigm Running on a Many-Core Neuromorphic Platform

Forno

Salvato

Macii

et al. 2021

JLPEA

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SpiNNaker is a neuromorphic hardware platform, especially designed for the simulation of Spiking Neural Networks (SNNs). To this end, the platform features massively parallel computation and an efficient communication infrastructure based on the transmission of small packets. The effectiveness of SpiNNaker in the parallel execution of the PageRank (PR) algorithm has been tested by the realization of a custom SNN implementation. In this work, we propose a PageRank implementation fully realized with the MPI programming paradigm ported to the SpiNNaker platform. We compare the scalability of the proposed program with the equivalent SNN implementation, and we leverage the characteristics of the PageRank algorithm to benchmark our implementation of MPI on SpiNNaker when faced with massive communication requirements. Experimental results show that the algorithm exhibits favorable scaling for a mid-sized execution context, while highlighting that the performance of MPI-PageRank on SpiNNaker is bounded by memory size and speed limitations on the current version of the hardware.

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“…Ref. [4], [9], [10], [16]- [18]. However, hardware accelerators that focus on SbS have only been partially investigated so far [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Accelerating Spike-by-Spike Neural Networks on FPGA With Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation

et al. 2021

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Spiking neural networks (SNNs) represent a promising alternative to conventional neural networks. In particular, the so-called Spike-by-Spike (SbS) neural networks provide exceptional noise robustness and reduced complexity. However, deep SbS networks require a memory footprint and a computational cost unsuitable for embedded applications. To address this problem, this work exploits the intrinsic error resilience of neural networks to improve performance and to reduce hardware complexity. More precisely, we design a vector dot-product hardware unit based on approximate computing with configurable quality using hybrid custom floating-point and logarithmic number representation. This approach reduces computational latency, memory footprint, and power dissipation while preserving inference accuracy. To demonstrate our approach, we address a design exploration flow using high-level synthesis and a Xilinx SoC-FPGA. The proposed design reduces 20.5× computational latency and 8× weight memory footprint, with less than 0.5% of accuracy degradation on a handwritten digit recognition task.

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A Review of Spiking Neuromorphic Hardware Communication Systems

Cited by 91 publications

References 39 publications

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

PageRank Implemented with the MPI Paradigm Running on a Many-Core Neuromorphic Platform

Accelerating Spike-by-Spike Neural Networks on FPGA With Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation

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