2011 3rd International Conference on Electronics Computer Technology 2011
DOI: 10.1109/icectech.2011.5942075
|View full text |Cite
|
Sign up to set email alerts
|

A review on power optimization of linear feedback shift register (LFSR) for Low power built in self test (BIST)

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2013
2013
2022
2022

Publication Types

Select...
4
2

Relationship

0
6

Authors

Journals

citations
Cited by 12 publications
(1 citation statement)
references
References 9 publications
0
1
0
Order By: Relevance
“…By using this method, 20% of maximum power and 30% of average power reduction is achieved. In a modified clock scheme proposed in [8] [9], two n/2-bit LFSRs are used in building n-bit LFSR. Mostly, a clock with half of its normal speed is used in activation of one portion of the D flip-flops in the TPG during one clock cycle.…”
Section: A Power Optimization Techniquesmentioning
confidence: 99%
“…By using this method, 20% of maximum power and 30% of average power reduction is achieved. In a modified clock scheme proposed in [8] [9], two n/2-bit LFSRs are used in building n-bit LFSR. Mostly, a clock with half of its normal speed is used in activation of one portion of the D flip-flops in the TPG during one clock cycle.…”
Section: A Power Optimization Techniquesmentioning
confidence: 99%