A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS

Abstract

Panasonic, Cupertino, CAAll-digital phase-locked loops (ADPLLs) have recently become more popular as possible alternatives to conventional analog charge-pump-based PLLs [1]. Currently, most of the ADPLLs are based on a time-to-digital converter (TDC) utilizing inverter delay chains. There have been tremendous efforts to improve TDC performance, i.e., maximizing resolution and reducing power consumption, but they normally require additional complex circuits.Recently, the ring-oscillator-based ADPLLs have been presented in [2,3], which substantially simplify the architecture of ADPLL by eliminating inverter delay chains as well as calibration routines for period normalization that are required for the conventional TDC-based approach. However, due to the poor phase noise of the ring oscillators and the limited time resolution available from inverters, those techniques are not applicable to modern wireless systems with stringent phase noise requirements.In this work, we demonstrate a low-phase-noise 4GHz ADPLL with an embedded phase-to-digital converter (PDC), where the rotary traveling-wave oscillator (RTWO) [4] is used as a digitally controlled oscillator (DCO). By using 32 multiphase signals available from the RTWO, the analog phase information is naturally converted into the digital domain, which simplifies the ADPLL architecture while maintaining excellent phase noise both close-in and far-out.The typical circuit topology of the RTWO is illustrated in Fig. 5.7.1. A cross-connected differential transmission line forms a closed-loop to establish the required feedback. In the steady-state, only one direction of the signal is sustained and propagates along the transmission line. By tapping off the signals from different positions on the resonator, multiphase signals are easily obtained. Since the RTWO relies on the resonance of the distributed LC-tank, unlike ring oscillators, it can achieve excellent phase noise. Figure 5.7.2 shows the architecture of the proposed ADPLL. Multiphase signals from the RTWO are latched by the reference clock (REF), which provides a pseudo-thermometer code representing the instantaneous phase of oscillation. The bubble correction block eliminates the unexpected bubbles in the outputs. By barrel shifting the outputs with the rotator block, the delay between the fractional phase and the integer phase (counter outputs) are adjusted within fractional phase resolution. This is achieved by minimizing the spurs at the ADPLL output. The remaining skew potentially causes an instantaneous 2π error, but this is corrected by the glitch correction algorithm [5]. The direction of the oscillation is determined by comparing the phase between non-adjacent taps. Based on the direction, either a clockwise look-up table (LUT) or a counter-clockwise LUT is selected to decode the pseudo-thermometer code into binary code. The coefficients of the LUT used to suppress the fractional spurs due to nonlinearity of the PDC are estimated by measuring the statistical distribution of the fractional phase outputs [6]. ...

Analysis of Frequency Synthesisers for Multistandart Wireless Transceiver / Dažnio Sintezatorių Daugiastandarčiams Bevielio Ryšio Siųstuvams Ir Imtuvams Analizė

“…Galiai skaitmeniniais projektavimo įrankiais įgyvendintuose dažnio sintezatoriuose sumažinti naudojami žiediniai generatoriai (Liu et al 2013;Takinami et al 2011).…”

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

“…To obtain the knowledge of the signal rotation direction of the traditional ROA, a direction detector used to facilitate the design [27], which is similar to a phase detector in a delay locked loop designed for high-frequency usage [28], [29]. To be used in the design of the traditional ROA, the direction detector is equipped with the function of resetting the synchronization process when it detects the signal direction is undesirable.…”

“…Previous research [30] shows that accumulation-mode MOS varactors outperform the other two types of varactors in terms of power dissipation, phase noise, and area, which has been widely used in PLL design [27], [31]. Approximating the loading capacitance for each tapping point to be 1 pF, to direct the ring to rotate in a desired rotation direction, the maximum capacitance provided by the varactor should at least be C max = 1 pF.…”

High-performance, low-power resonant clocking

“…Back-to-back inverters are connected to this parallel loop to compensate for the [12,15,21,30,35,39], including zero clock skew operation [14,16], interconnect modeling [13], frequency estimation [32], phase estimation and control [31,34,38], phase noise [29] and variation-sensitivity [33]. Prototype designs have been demonstrated [28,37]. At least one company has a commercial product to support rotary clocking [23].…”