A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs

Abstract

With the reduction in feature size, transient errors start to play an important role in modern embedded systems. It is therefore important to make fault-tolerance a first-class citizen in embedded system design. Fault-tolerance patterns are techniques to make an application fault-tolerant. Not only do fault-tolerance patterns affect the quality of the embedded system (like performance, energy and cost), but there also are many ways of applying them. In this paper, we present the SAFE simulation framework that supports the early exploration of the different possibilities to apply faulttolerance patterns to MPSoC-based embedded multimedia systems. The SAFE model incorporates fault injection, detection and correction. As a result, a Pareto front can be obtained that not only shows the trade-off between metrics like performance, energy, cost, but also captures reliability metrics like frame drops due to soft errors and the number of unresolvable faults.

DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

“…30.5.1, recognizing separate application and architecture models. SESAME has also been extended to allow for capturing power consumption behavior and reliability behavior of MPSoC platforms [44,45,50]. The layered infrastructure of SESAME's modeling and simulation environment is shown in Fig.…”

Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs

“…Analysis [2] none static makespan [3] FI/FD/FT static makespan [4] none dynamic simulation [5] FI/FT dynamic probabilistic [6] failure probability dynamic worst-case FT: Fault-Tolerance, FD: Fault-Detection, FI: Fault-Ignorance.…”

“…1 The main challenge in adopting this mixed-criticality scheduling is the analysis and guarantees on the WCRT. Previous approaches (see Table 1) use ordinary scheduling policies and base their analysis on either statically determined makespan [2], [3] or do not guarantee the WCRT [4], [5] relying on simulation or probabilistic analysis. The static scheduling may simplify the optimization complexity but it is inefficient in terms of resource usage [8], and too rigid to be reactive to dynamic system mode changes.…”

“…That is, the nominal execution time (k = 0) is the case when there is no fault, while the critical case includes the re-execution and variations in wcet ′ . This is a well-known source of wcet variation, considered in fault-tolerant system designs like [2], [4] and mixed-criticality systems like [5].…”

Multi-objective redundancy hardening with optimal task mapping for independent tasks on multi-cores

“…Since different fault-tolerant techniques are usually characterized by different time and space overheads, there is an optimization trade-off in task hardening, i.e., determining one of the fault-tolerant techniques (e.g., DMR or TMR) for each task. This trade-off, together with the traditional optimization in task mapping, i.e., mapping each task to one of the cores, makes the design of fault-tolerant multi-cores very challenging (Das et al 2014;Gan et al 2012;Khosravi et al 2014;Pop et al 2009;Stralen and Pimentel 2012). It is notable that replication-based task hardening will introduce new tasks, i.e., replicas, into the system, and these replicas should be mapped as well.…”