A scalable bootloader and debugger design for an NoC-based multi-processor SoC

Abstract

This paper presents bootloader and debugger architectures that are designed for an NoC-based Multiprocessor System On-Chip (MPSoC). An MPSoC demands scalable bootloader and debugger architectures, especially with the increasing of the number of the processor cores. The proposed bootloader and debugger designs utilize the NoC interconnect network to distribute data to and from the cores. With this design approach, the bootloader and debugger require relatively small hardware overhead and are able to fully utilize the benefit of the NoC architecture's scalability.

Multicore development environment for embedded processor in arduino IDE

“…The RUMPS401 current consumption is around 30mA with all cores running, and around 13uA when all cores are put to sleep [21]. It provides program uploading via scalable bootloader design which utilizes the in-chip hardware bootloader and software bootloader for distributing programs to individual cores via NoC [22]. One of the RUMPS401 core, the IO Core [23] is designed to run in two modes, the first for aiding the bootloading process, and second to run its normal functionality.…”

Minimalistic SDHC-SPI hardware reader module for boot loader applications

“…This first stage (also called pre-loader) is a small piece of code that is not often updated, as the most firmware updates are usually carried out in the second stage. Multiple approaches and implementations propose different methods and/or methodologies [5][6][7] for the boot loader process depending on the application. The common principle is a boot loader with two important features: low-footprint area and the ability to upload firmware updates [6].…”