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This paper presents bootloader and debugger architectures that are designed for an NoC-based Multiprocessor System On-Chip (MPSoC). An MPSoC demands scalable bootloader and debugger architectures, especially with the increasing of the number of the processor cores. The proposed bootloader and debugger designs utilize the NoC interconnect network to distribute data to and from the cores. With this design approach, the bootloader and debugger require relatively small hardware overhead and are able to fully utilize the benefit of the NoC architecture's scalability.

Network-on-Chip (NoC) has been proposed as a solution for the communication challenges of Multi-ProcessorSystem-on-chip (MPSoC) design in nanoscale technologies and it has better reusability and scalability. However along with the advantages of any communication parameter follow its disadvantages. Most state-of-the-art NoC architecture and their design flows is optimized for a single application, and no single NoC can provide optimal performance across a wide range of applications. In this research, a reconfigurable and adaptable Network-on-Chip architecture is proposed. Adaptive routing components are designed to enable the router to select a path with less congestion. Parameterize file is designed to enable the NoC to be reconfigured and scalable.

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