A Scalable DCO Design for Portable ADPLL Designs

This paper reports two distinct architectures for digitally-controlled oscillators (DCOs) utilizing MOS varactor, designed in TSMC 180 nm CMOS technology. The first DCO design employs a CMOS inverter, while the second design features a Three-Transistors (3T) NAND gate as a delay stage inverter. Using these delay stages, three-bit, five-bit, and seven-bit controlled DCO circuits have been designed. For the inverter-based DCO circuit, the frequency spans from 4.844 to 2.708 GHz, 2.523 to 0.853 GHz, and 1.364 to 0.253 GHz, with a power consumption of 0.958 mW, 1.597 mW, and 2.236 mW for three-bit, five-bit, and seven-bit DCO variants, respectively. Further, the 3T-NAND gate-based DCO circuit exhibits oscillation frequencies ranging from 2.024 to 0.517 GHz, 0.867 to 0.131 GHz, and 0.341 to 0.033 GHz, with the resulting power consumption of 0.335 mW, 0.559 mW, and 0.782 mW. Equally significant, the proposed inverter-based DCO attains phase noise of − 102.61 dBc/Hz@1MHz, − 99.65 dBc/Hz@1MHz, and − 117.54 dBc/Hz@1MHz, accompanied by corresponding figures of merit (FoM) 174.94 dBc/Hz, 161.27 dBc/Hz, and 165.10 dBc/Hz for three-bit, five-bit, and seven-bit control words, respectively. For the 3T-NAND gate-based DCO, phase noise levels register at − 93.51 dBc/Hz@1MHz, − 113.07 dBc/Hz@1MHz, and − 106.96 dBc/Hz@1MHz, with FoM values of 160.23 dBc/Hz, 166.70 dBc/Hz, and 150.30 dBc/Hz for three-bit, five-bit, and seven-bit DCO variants, respectively. The comprehensive analysis of the proposed DCOs demonstrates the power supply variations, phase noise deviations, and frequency variations. The reported DCOs perform better with regard to output frequency range, power consumption, and overall FoM.

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