A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

Hasan, Mehedi; Islam, Sharnali; Hossain, Mainul; Zaman, Hasan U.

doi:10.1002/cta.3109

Cited by 14 publications

(10 citation statements)

References 26 publications

(27 reference statements)

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“…Therefore, under D cnt variations, the lower the power, the lower the sensitivity of the circuits. Table 7 shows that for the chirality vectors of (13, 0), (23,0), and (32, 0), the proposed circuit with 0.179 μW, 0.3291 μW, and 0.6298 μW, respectively, resulted in lower PDP and PDAP compared with other circuits, even over those with higher speed. The Reversible-1 and Reversible-2 are not able to operate under considering 0.424 V of V th.…”

Section: Th (D Cnt ) and Number Of Tubes Variationmentioning

confidence: 99%

“…The opposite transistor, T 6 , is used for this purpose. In addition, SR transistors are becoming increasingly critical due to the lack of V DD and GND in the XNOR circuit, which is called power‐ground‐free 23 . Therefore, it is necessary to apply inverted signals (so‐called fresh) to transmit the signals to the output with enough strength.…”

Section: Proposed Circuitsmentioning

confidence: 99%

“…In addition, SR transistors are becoming increasingly critical due to the lack of V DD and GND in the XNOR circuit, which is called power-ground-free. 23 Therefore, it is necessary to apply inverted signals (so-called fresh) to transmit the signals to the output with enough strength. Also, contributed to this feature, there is no direct path between V DD and GND, so it is expected that this gate has approximately zero static power, which has a large contribution in reducing the power consumption of the entire circuit.…”

Section: Proposed 1-bit Comparatormentioning

confidence: 99%

“…CNTFETs are tunable with their V th , so different chirality vectors of (13, 0), (23,0), and (32, 0) which lead to 1.014 nm, 1.794 nm, and 2.496 nm as CNT diameter (D CNT ) are considered, and the transistors experienced 0.424 V, 0.239 V, and 0.172 V as V th , respectively, as shown in Table 7.…”

Section: Th (D Cnt ) and Number Of Tubes Variationmentioning

confidence: 99%

See 3 more Smart Citations

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Circuit Theory & Apps

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Summary The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs.

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Section: Th (D Cnt ) and Number Of Tubes Variationmentioning

confidence: 99%

Section: Proposed Circuitsmentioning

confidence: 99%

Section: Proposed 1-bit Comparatormentioning

confidence: 99%

Section: Th (D Cnt ) and Number Of Tubes Variationmentioning

confidence: 99%

See 2 more Smart Citations

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Circuit Theory & Apps

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show abstract

“…Obviously, despite the reduction in the number of transistors to 18, another created obstacle while using GDI in an FA cell is the strong dependence of the circuit on the transistor‐sizing issue so that swing restoration can be executed in charging sensitive node capacitors. A 22‐transistor FA is presented in [35] which has 3 modules of XOR‐XNOR (as the most critical gate) and a MUX for Sum as well as a separate carry generation circuit. The high number of internal nodes makes the circuit very sensitive to process variation, high power consumption, and low speed.…”

Section: Introductionmentioning

confidence: 99%

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Sadeghi

Shiri

Rafiee

et al. 2022

IET Circuits, Devices & Syst

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A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.

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Design of an automatic gain control loop for high speed communication

Chowdhury

Hasan

2022

Circuit Theory & Apps

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This paper presents the design of an automatic gain control (AGC) loop for high-speed communication systems, which can be used in wired, wireless, or optical receiver. The design is performed in 130 nm SiGe BiCMOS technology. A Gilbert cell-based variable gain amplifier is designed, which shows approximately linear gain control with respect to the gain control voltage. The variable gain amplifier is followed by two fixed gain cascode amplifiers. Then, a full wave rectifier-based peak detector is designed and analyzed. To reduce the peak detector error, a compensation technique is applied. Finally, an operational amplifier is designed, which is used as voltage adder and comparator.The designed AGC loop is simulated with sinusoidal and pseudorandom binary sequence (prbs) input signal with high frequency signal of 1 to 30 GHz.The simulation results of the AGC loop show that a gain tuning range of 47 dB (À7 to 40 dB) is obtained in this design. It is also seen that the reference signal can be varied from 50 to 200 mV. This AGC works in the input voltage signal range between 3 mV peak and 230 mV peak, and the power dissipation of is 79 mW. K E Y W O R D Sautomatic gain control, fixed gain amplifier, high efficiency power amplifier, peak detector, variable gain amplifier

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A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module

Cited by 14 publications

References 26 publications

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Design of an automatic gain control loop for high speed communication

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