We use infrared thermal imaging and electrothermal simulations to find that localized Joule heating in graphene field-effect transistors on SiO(2) is primarily governed by device electrostatics. Hot spots become more localized (i.e., sharper) as the underlying oxide thickness is reduced, such that the average and peak device temperatures scale differently, with significant long-term reliability implications. The average temperature is proportional to oxide thickness, but the peak temperature is minimized at an oxide thickness of ∼90 nm due to competing electrostatic and thermal effects. We also find that careful comparison of high-field transport models with thermal imaging can be used to shed light on velocity saturation effects. The results shed light on optimizing heat dissipation and reliability of graphene devices and interconnects.

ABSTRACT:We study graphene nanoribbon (GNR) interconnects obtained from graphene grown by chemical vapor deposition (CVD). We report low-and high-field electrical measurements over a wide temperature range, from 1.7 to 900 K. Room temperature mobilities range from 100 to 500 cm 2 V -1 s -1 , comparable to GNRs from exfoliated graphene, suggesting that bulk defects or grain boundaries play little role in devices smaller than the CVD graphene crystallite size. At high-field, peak current densities are limited by Joule heating, but a small amount of thermal engineering allows us to reach ~2 × 10 9 A/cm 2 , the highest reported for nanoscale CVD graphene interconnects. At temperatures below ~5 K, short GNRs act as quantum dots with dimensions comparable to their lengths, highlighting the role of metal contacts in limiting transport. Our study illustrates opportunities for CVD-grown GNRs, while revealing variability and contacts as remaining future challenges.

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Abstract-We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-κ dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 μs, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/µm. In addition, using modeling and capacitancevoltage measurements we extract charge trap densities up to 10 12 cm -2 in the top gate dielectric (here Al2O3). Our study illustrates important time-and field-dependent imperfections of top-gated GFETs with high-κ dielectrics, which must be carefully considered for future developments of this technology.

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